Microchip Technology Inc.

Andrew Alexander Taylor

Justin Sato

Bomy A Chen

Yaojian Leng

Janet Vanderiet

Bonnie Hamlin

An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a 'shock plate' (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond

A method for manufacturing a thin film resistor (TFR) module includes forming a TFR element over a substrate; annealing the TFR element to reduce the temperature coefficient of resistance (TCR) of the TFR element; and after forming and annealing the TFR element, forming a pair of conductive TFR heads in contact with the TFR element. By forming the TFR element before the TFR heads, the TFR element may be annealed without affecting the TFR heads, and thus may be formed from various materials with different annealing properties, e.g., SiCCr and SiCr. Thus, the TFR element may be annealed to achieve a near 0 ppm TCR, without affecting the later-formed TFR heads. The TFR module may be formed using a damascene CMP approach and using only a single added mask layer. Further, vertically-extending 'ridges' at edges of the TFR element may be removed or eliminated to further improve the TCR performance.

Thin-film resistor (TFR) formed under a metal layer and method of fabrication

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A semiconductor process for providing a metal layer uses the following steps: A barrier dielectric layer is deposited on a semiconductor layer comprising an exposed metal line. A via layer is formed on top of the barrier dielectric layer comprising at least one via. A non-conformal film is deposited on top of the via layer thereby forming a void in the at least one via, and at least one trench is etched into the non-conformal film thereby opening the void, and creating a dual-damascene layer.

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Portland, OR, United States of America

Andrew Alexander Taylor