Lucent Technologies Inc.

Agere Systems Inc.

Intel Mobile Communications Gmbh

Andrew A Wang

Ravi Jammula

Mark Ernest Thierbach

Lothar Winkler

Michael J Weber

A method, system, and apparatus for managing a plurality of cipher processor units. A cipher module may receive a cipher instruction indicating a cipher algorithm to be used. The cipher module may identify a cipher processing unit of the plurality of cipher processing units associated with the cipher algorithm. The cipher module may execute the cipher instruction using the cipher processing unit and the common register array. The cipher module may store a state of a common register array to be used by the cipher processing unit of the plurality of cipher processing units.

Low-power multi-standard cryptography processing units with common flip-flop/register banks

An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test bus between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.

Optimum timing of write and read clock paths

A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a plurality of buses, each of the buses having multiple data lines for transferring data based on the data transfer protocols, a multiplexer coupled to the plurality of buses for multiplexing the data onto parallel lines and a CRC signature compactor coupled to the parallel lines for receiving the data. The CRC signature compactor compresses the data and (1) provides a fault-free signature representative of the data in a known fault-free chip, and (2) provides another signature representative of the data in a chip under test, wherein the two signatures are compared to determine whether a fault exists in the chip under test.

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Wescosville, PA, United States of America

Andrew A Wang