International Business Machines Corporation

Globalfoundries Inc.

Other

Andrew A Turner

Kirk David Peterson

John B DeForge

Eberhard Engler

Sean Michael Carey

Robert C Redburn

Christian Jacobi

Alper Buyuktosunoglu

Herbert Lei Ho

Babar Ali Khan

William Vincent Huott

Mary Prilotski Kusko

Phillip John Restle

Tobias Webel

Cathryn Jeanne Christiansen

Edward C McCain

Kennedy K Cheruiyot

Pradeep Bhadravati Parashurama

Alejandro Alberto Cook Lobo

Kevin P Low

Karl Evan Smock Anderson

Andrew H Norfleet

Jennifer E Appleyard

Daniel Kiss

Isidore G Bendrihem

Ian Krispin Carmichael

Alain G Rwabukamba

Robert J Gauthier, Jr

Terence B Hook

John Edward Sheets, Ii

Souvick Mitra

Franco Motika

JunJun Li

John Edward Barth, Jr

John G Torok

Tom C Lee

K Paul Muller

Noah B Singer

Martin Eckert

Gregory Scott Still

James Paul Di Sarro

Gerard M Salem

Hubert Harrer

Sridhar H Rangarajan

Eugene R Atwood

Gary William Maier

Miles C Pedrone

Joe L Smith

Jeffrey Scott Zimmerman

Eric Jason Fluhr

Nathaniel R Chadwick

Richard W Oldrey

John E Barth

Christopher Raymond Conklin

Frank William Angelotti

Gary Alan Peterson

Paul Jacob Logsdon

Kenneth Lee Christian

Theresa Newton

Rohan A Jones

Daniele Di Genova

Michael D Campbell

Hunter Feng Shi

Neil A Malek

Dermot Weldon

Paul Wright, Iii

Lebraun Premo

Ken Premo

Nicholai L'Esperance

Stephanie Lehrer

Adisun Wheelock

Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Dynamic guard band with timing protection and with performance protection

Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

Aspects of the invention include systems and methods directed to a portable chip tester. A non-limiting example of a system includes a housing, a printed circuit board mounted on the housing, in which the printed circuit board includes a first interface operable to permit electrical communication between the printed circuit board and a device under test. The system further includes a mount operable to enable an electrical connection with an integrated circuit, in which the integrated circuit is operable to manage testing the device under test under a testing protocol. The system further includes a power supply and a software platform that includes a memory having computer readable instructions and one or more processors for executing the computer readable instructions. The computer readable instructions controlling the processors to perform operations including directing the integrated circuit to manage testing of the device under test pursuant to the testing protocol.

Portable chip tester with integrated field programmable gate array

Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.

Tunable power save loop for processor chips

Frame or mat

A method and performance-screen ring oscillator (PSRO) test structure for designing, testing, and manufacturing a VLSI device. The performance-screen ring oscillator (PSRO) test structure comprises a ring oscillator having a plurality of stages; one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; and one or more multiplexers, each multiplexer being coupled to at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load.

Performance-screen ring oscillator with switchable features

According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Testing mechanism for a proximity fail probability of defects across integrated chips

Methods, systems and computer program products for generating a functional logic cone signature for circuit analysis are provided. Aspects include for each of a plurality of portions of a circuit diagram of a circuit, tracing the respective portion of the circuit diagram to identify circuit components associated with the respective portion of the circuit diagram from a starting latch to one of one or more source latches. Circuit components include circuit elements and circuit connections. Aspects include generating an ASCII representation of the respective identified circuit components for each of the plurality of portions of the circuit diagram of the circuit. Aspects include generating a plurality of hash values by applying a hashing function to each ASCII representation. Each hash value corresponds to one of the plurality of portions of the circuit diagram. Aspects also include storing the hash values in a data structure.

Functional logic cone signature generation for circuit analysis

Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.

Semiconductor power and performance optimization

Disclosed herein is a method for failure signature detection in a semiconductor comprising generating defect signatures for failing latches from a plurality of integrated circuit chips; generating a latch to mask relationship for the failing latches; generating maximally descriptive masks into identities; generating a list of identities for comparison; determining commonalities between the lists of identities; and generating details about differences and commonalities within the defect signatures.

Method for enhanced semiconductor product diagnostic fail signature detection

In various embodiments, the disclosure relates to a hardware test generation environment for developing test tool analysis workflows. Configurable flow files direct the steps, procedures, and data acquisitions associated with device testing and can be flexibly deployed and updated in connection with a variety of electronic test tools. The hardware test generation environment may operate separately from the hardware test execution environment allowing device test protocols and methodologies to be independently developed, improved, and validated.

Method and apparatus for offline supported adaptive testing

A method, system, and/or computer program product of scanning of an integrated circuit including chiplets to isolate fault locations is provided herein. The scanning of the integrated circuit includes providing, by a pervasive of the integrated circuit, an input to the chiplets. Each of the chiplets can include a pervasive satellite, a multiplexer, and latches. The scanning of the integrated circuit includes also scanning, by each pervasive satellite of the chiplets, data based on the input via the multiplexer into the latches to produce scan data for each of the chiplets. The scanning of the integrated circuit also includes comparing, by the pervasive of the integrated circuit, the scan data of each of the chiplets to expectant data stored on the pervasive to isolate the fault locations.

Optimized chain diagnostic fail isolation

Embodiments are directed to a method of mitigating voltage noise events. The method includes detecting the presence of a voltage noise event at the integrated circuit device. Thereafter, one or more local clock buffers (LCBs) is selected for dampening. A type of dampening is selected for the LCBs. Finally, the dampening is applied to the LCB while the voltage noise event is occurring.

Dynamic noise mitigation in integrated circuit devices using local clock buffers

Technical solutions are described for optimizing a set of test configurations used for testing an electronic circuit that includes latches. An example method includes receiving a test configuration that includes settings that initiate a set of predetermined input values and corresponding expected output values. The method also includes evaluating the test configuration by executing the electronic circuit according to the test configuration and recording parametric data during the execution, where the parametric data is representative of switching activity of the latches in the electronic circuit. The evaluation includes analyzing the parametric data to identify presence of a predetermined pattern in the switching activity and selecting the test configuration based on the predetermined pattern being absent/present in the switching activity.

Optimizing generation of test configurations for built-in self-testing

Growing community of inventors

Milton, VT, United States of America

Andrew A Turner