California Institute of Technology

United States of America as Represented by the Administrator of Nasa

Andrew A Gray

Tsun-Yee Yan

Clayton M Okino

Meera Srinivasan

Payman Arabshahi

Gerald J Grebowsky

A reconfigurable architecture for wireless digital data and voice communications is provided for ad hoc and/or an ad hoc collection of organized networks. At least some user wireless communication units serve as relay stations for other users units, enabling any user within the range of another, participating user to gain access to the local- and wider-area networks in a multihop process. Reconfigurable hardware enables dynamic protocol 'preferencing', and easy upgrades to potential future wireless protocol standards. Power-efficient communication takes place by using multihop radio communication at the local level and high-speed point-to-point links (e.g. fiber, satellite) at the global level. Microcells within a network community are aggregated into cells by use of a local-area-network (LAN) backbone of higher speed wireless and/or wired connections. Every time a microcell connects to the wireless backbone, microcells or individual users in surrounding blocks can also connect to the network.

Reconfigurable protocols and architectures for wireless networks

Disclosed is a method of providing signal processing operations, including convolution/filtering, where each parallel stream is processing signals at a lower rate than the signal data rate itself while still resulting in an overall signal processing rate suitable for high rate signal processing. This allows devices with a lower signal processing rate to be used in the parallel processing paths, avoiding many of the problems facing prior art high data rate signal processing. The invention converts a signal from the time domain to the frequency domain and takes advantage of associative and communicative properties of data processing to perform signal processing operations in parallel.

Method and apparatus for parallel signal processing

A method to demodulate BPSK or QPSK data using clock rates for the receiver demodulator of one-fourth the data rate. This is accomplished through multirate digital signal processing techniques. The data is sampled with an analog-to-digital converter and then converted from a serial data stream to a parallel data stream. This signal processing requires a clock cycle four times the data rate. Once converted into a parallel data stream, the demodulation operations including complex baseband mixing, lowpass filtering, detection filtering, symbol-timing recovery, and carrier recovery are all accomplished at a rate one-fourth the data rate. The clock cycle required is one-sixteenth that required by a traditional serial receiver based on straight convolution. The high rate data demodulator will demodulate BPSK, QPSK, UQPSK, and DQPSK with data rates ranging from 10 Mega-symbols to more than 300 Mega-symbols per second. This method requires less clock cycles per symbol tan traditional serial convolution techniques.

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Pasadena, CA, United States of America

Andrew A Gray