Eagle Technology, LLC

Andres M Gonzalez

Michael T DeRoy

Michael T De Roy

William A Marquart

Jay S Nelson

Phillip K Nickel

Tena M Hochard

Bill Marquart

Phill Nickel

Marvin D Miller

Scott Nelson

David Cure

Systems and methods for applying solder to a pin. The methods comprising: disposing a given amount of solder on a non-wettable surface of a planar substrate; aligning the pin with the solder disposed on the non-wettable surface of the planar substrate; inserting the pin in the solder; and/or performing a reflow process to cause the solder to transfer from the planar substrate to the pin.

Systems and methods for providing an interface on a printed circuit board using pin solder enhancement

Systems and methods for applying solder to a pin. The methods comprising: disposing a given amount of solder on a non-wetable surface of a planar substrate; aligning the pin with the solder disposed on the non-wetable surface of the planar substrate; inserting the pin in the solder; and performing a reflow process to cause the solder to transfer from the planar substrate to the pin.

Systems and methods for providing a soldered interface between a circuit board and a connector pin. The methods comprise: using a jet paste dispenser to apply first solder into a plated contact cavity formed in the circuit board; using a stencil screen printer to apply second solder (a) over the plated contact cavity which was at least partially filled with the first solder by the jet paste dispenser and (b) over at least a portion of a pad surrounding the plated contact cavity; inserting the connector pin in the plated contact cavity such that the connector pin passes through the second solder and extends at least partially through the first solder; and performing a reflow process to heat the first and second solder so as to create a solder joint between the circuit board and the connector pin.

Systems and methods for providing a soldered interface on a printed circuit board having a blind feature

Systems and methods for providing a PWB. The methods comprise: forming a Core Substrate ('CS') a First Via ('FV') formed therethrough; disposing a First Trace (&#x201c;FT&#x201d;) on an exposed surface of CS that is in electrical contact with FV; laminating a first HDI substrate to CS such that FT electrically connects FV via with a Second Via (&#x201c;SV&#x201d;) formed through the first HDI substrate; disposing a Second Trace (&#x201c;ST&#x201d;) on an exposed surface of the first HDI substrate that is in electrical contact with SV; and laminating a second HDI substrate to the first HDI substrate such that ST electrically connects SV to a Third Via (&#x201c;TV&#x201d;) formed through the second HDI substrate. SV comprises a buried via with a central axis spatially offset from central axis of FV and SV. FV and SV have diameters which are smaller than TV's diameter.

Systems and methods for providing a high speed interconnect system with reduced crosstalk

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Melbourne, FL, United States of America

Andres M Gonzalez