International Business Machines Corporation

Andres Herrera

Omar Cardona

Pedro V Torres

Rafael Velez

Herman Dietrich Dierks

Kiet Hien Lam

Bernard A King-Smith

Processing data packets from a receive queue is provided. It is determined whether packets are saved in a pre-fetched queue. In response to determining that packets are not saved in the pre-fetched queue, a number of packets within the receive queue is determined. In response to determining the number of packets within the receive queue, it is determined whether the number of packets within the receive queue is greater than a number of packets called for by an application. In response to determining that the number of packets within the receive queue is greater than the number of packets called for by the application, an excess number of packets that is above the number of packets called for by the application is saved in the pre-fetched queue. An indication is sent to the application of the excess number of packets. The predetermined number of packets is transferred to the application.

Processing data packets from a receive queue in a remote direct memory access device

A mechanism is provided in a data processing system for shared buffer affinity for multiple ports. The mechanism configures a physical first-in-first-out (FIFO) buffer with a plurality of FIFO segments associated with a plurality of network ports. The plurality of network ports share the physical FIFO buffer. The mechanism identifies a FIFO segment under stress within the plurality of FIFO segments. The mechanism reconfigures the physical FIFO buffer to assign a portion of buffer space from a FIFO segment not under stress within the plurality of FIFO segments to the FIFO segment under stress.

FIFO affinity for multiple ports

Mechanisms for controlling rollover or reset of hardware performance counters in the data processing system. A signal indicating that a rollover or reset of a first hardware performance counter has occurred is received and it is determined if the first hardware performance counter is analytically related to one or more second hardware performance counters based on defined ganged hardware performance counter sets. A signal is sent to each of the one or more second hardware performance counters in response to a determination that the first hardware performance counter is analytically related to the one or more second hardware performance counters. Each of the one or more second hardware performance counters is reset to an initial value in response to the one or more second hardware performance counters receiving the signal from the ganged hardware performance counter rollover/reset logic.

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Austin, TX, United States of America

Andres Herrera