Telefonaktiebolaget Lm Ericsson (publ)

Infineon Technologies Ag

Btg International Limited

Andrej Litwin

Sven Erik Mattisson

Anders S&ouml;derb&auml;rg

Ola Pettersson

Ted Johansson

Torkel Bengt Arnborg

Hans Erik Norstrom

Anders Soderbarg

Lars Montelius

Peter Olofsson

Torbjorn G I Ling

Johan Sj&ouml;str&ouml;m

Ganesh Kathiresan

Anders Dunkars

Paul Andersson

An RF front-end receiver comprises a low noise amplifier and a local oscillator driver, which are connected to respective input ports of a mixer which comprises a first and second transistor with gates coupled to one output terminal, a third and fourth transistor with gates coupled to the other output terminal, a fifth and sixth transistor with gates coupled to respective output terminal of the local oscillator driver, the sources of the first and third transistors coupled to the drain of the fifth transistor, the sources of the second and fourth transistor coupled to the drain of the sixth transistor, the sources of the fifth and sixth transistor coupled to ground, the drains of the first and fourth transistor coupled to one output terminal of a mixer output port, and the drains of the second and third transistor coupled to the other output terminal of the mixer output port.

RF front-end receiver

A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.

Device for ESD protection of an integrated circuit

A device for ESD protection of a high frequency circuit () of a semiconductor device comprises first () and second () p-type and first () and second () n-type JFET's, wherein the first p-type JFET () is connected with its gate to a high voltage source, its source to an input/output pad () of the semiconductor device, and its drain to the source of the first n-type JFET (), the second p-type JFET () is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (), and its drain to an input/output terminal of the circuit (), the first n-type JFET transistor () is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor () is connected with its gate to ground (GND), and its source to the input/output pad ().

A monolithically integrated microwave amplifier device, comprises an input for receiving a microwave signal, a first power amplifier stage () having an input coupled to receive the microwave signal, an impedance matching network () coupled to an output of the first power amplifier stage, a second power amplifier stage () having an input coupled to the impedance matching network, and an output for outputting the microwave signal after having been amplified by the first and second power amplifier stages, wherein the first power amplifier stage is optimized to be supplied with a first supply voltage (), which is essentially lower than a second supply voltage (), with which the second power amplifier stage is optimized to be supplied. Preferably, the second stage is an end stage based on an LDMOS transistor, and the first stage is a driver stage based on a bipolar transistor.

Monolithically integrated power amplifier device

To protect a high-frequency integrated circuit () against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (), a semiconductor varistor () having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad () and the input/output terminal together with the integrated circuit ().

Arrangement for ESD protection of an integrated circuit

A digital radio transceiver integrated circuit includes MOS transistors with normal threshold voltages in the digital circuits, and with reduced threshold voltages in at least some of the analog RF components. This allows the transceiver to be reduced in size and weight, without requiring performance to be compromised.

Radio architecture

An array of nanometric dimensions consisting of two or more arms, positioned side by side, wherein the arms are of such nanometric dimensions that the beams can be moved or deformed towards or away from one another by means of a low voltage applied between the beams, whereby to produce a desired optical, electronic or mechanical effect. At nanometer scale dimensions structures previously treated as rigid become flexible, and this flexibility can be engineered since it is a direct consequence of material and dimensions. Since the electrostatic force between the two arms is inversely proportional to the square of the distance, a very considerable force will be developed with a low voltage of the order of 1-5 volts, which is sufficient to deflect the elements towards or away from one another. As preferred, the bulk of the element may comprise an insulating material, and an upper conductive layer is applied on the upper surface, where the element is formed by a nanolithography method such as nanoimprint lithography (NIL). Alternatively the elements may be formed completely of conductive material, where the elements are formed by a CMOS metalization process.

MEMS devices with voltage driven flexible elements

The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.

Integration of high voltage self-aligned MOS components

A method is disclosed for noise distribution in high resistivity substrates containing differential or balanced integrated circuitry obtaining a noise suppression by an introduction of noise distributors. Noise from an external noise source ( ) is made isotropic in relation to branches of a differential or balanced integrated circuitry by creating a low resistivity path adjacent to the differential or balanced integrated circuitry typically formed by two integrated transistors (A, B) or group of transistors. The low resistivity path in the general case is made symmetrical in relation to the integrated transistors thereby forming a noise distributor for distributing the noise evenly. The noise distributor then is formed as a floating substrate contact ( ) of the same doping kind as a substrate or a well within which the differential or balanced circuitry is contained. Furthermore the shape of the noise distributor will be optimized by simulations of the structure of the noise distributing low resistivity path, which structure does not need to be continuous as long as the low resistivity path is maintained.

Method for substrate noise distribution

A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighbouring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 &mgr;m. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 &mgr;m. The distances from the long sides of the rectangular area to the edges of the chip should be at least 50% and preferably 60% of the thickness of the chip to allow a good thermal flow out of the active rectangular area. A plurality of such very elongated active areas can be located on a single chip.

Power transistors for radio frequencies

A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schotty barriers or pn-hereto-barriers and distributing X particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputted layer. Finally the top wafer is thinned to provide a layer thickness suitable for the processing steps required in the manufacture of components.

Substrate for high frequency integrated circuits

The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires ( ) go perpendicularly to the gate and drain bonding wires ( ). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.

Method and device for interconnected radio frequency power SiC field effect transistors

A semiconductor integrated circuit comprises a substrate (,) of a first conduction type semiconductor material, an epitaxial layer (,) which is carried by the substrate (,) and which is of a second conduction type semiconductor material different to the first conduction type material, a well (,) of semiconductor material in the epitaxial layer and a semiconductor material, the epitaxial layer (,) being substantially depleted of charges is a region substantially beneath the well (,).

Integrated circuits

A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schottky barriers or pn-hetero-barriers and distributing the particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputtered layer. Finally the top wafer is thinned to provide a layer thickness suitable for the processing steps required in the manufacture of components.

Growing community of inventors

Danderyd, Sweden

Andrej Litwin