Advanced Micro Devices Corporation

Globalfoundries Inc.

Andrej Kocev

Alexander J Branover

Maurice B Steinman

Jay E Fleischman

R Stephen Polzin

Michael Haertel

Kai Troester

Neil N Marketkar

Tim J Wilkens

Johnny C Chu

Michael W Long

Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.

Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines

A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.

Function based dynamic power control

A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.

ECC implementation in non-ECC components

A processor system () includes a central processing unit () and a prefetch engine (). The prefetch engine () is coupled to the central processing unit (). The prefetch engine () is configured to detect, when data associated with the central processing unit () is read from a memory (), a stride pattern in an address stream based upon whether sums of a current stride and a previous stride are equal for a number of consecutive reads. The prefetch engine () is also configured to prefetch, for the central processing unit (), data from the memory () based on the detected stride pattern.

Technique for prefetching data based on a stride pattern

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York, ME, United States of America

Andrej Kocev