Nxp B.v.

Nytell Software LLC

Andrei Sergeevich Terechko

Manish Garg

Jan Hoogerbrugge

Ghiath Al-Kadi

Han Raaijmakers

Abraham Karel Riemens

Klaas Brink

Sainath Karlapalem

Gerardo Henricus Otto Daalderop

Johannes Martinus Bernardus Petrus Van Doorn

Gerardo H O Daalderop

Johannes Van Doorn

Jochen Seemann

Ali Osman Örs

Johannes Martinus Bernadus Petrus Van Doorn

A packet is transmitted from a remote device over a communication network. A fragment detector detects one or more fragments in a field of the packet, where the field is associated with a session layer or higher abstraction layer of an open systems interconnect (OSI) model. Fragment information is extracted from the packet which indicates one or more of a last fragment index associated with a last fragment of one or more fragment in the packet and a fragment count indicative of a number of fragments associated with a message which is fragmented. Interrupts associated with the packet with other interrupts associated with other packets are coalesced based on one or more of the last fragment index and the fragment count.

Coalescing interrupts based on fragment information in packets and a network controller for coalescing

A method, system and device are disclosed for determining safety conflicts in redundant subsystems of autonomous vehicles. Each redundant subsystem calculates a world model or path plan, including locations, dimensions, and orientations of moving and stationary objects, as well as projected travel paths for moving objects in the future. The travel paths and projected future world models are subsequently compared using a geometric overlay operation. If at future time moments the projected world models match within predefined margins, the comparison results in a match. In case of a mismatch at a given future moment between projected world models, a determination is made as to whether the autonomous vehicle and all road users in this future moment are safe from collision or driving off the drivable space or road based on a geometric overlay operation.

Safety-aware comparator for redundant subsystems in autonomous vehicles

A method, apparatus, article of manufacture, and system are provided for detecting hardware faults on a multi-core integrated circuit device by executing runtime software-based self-test code concurrently on multiple processor cores to generate a first set of self-test results from a first processor core and a second set of self-test results from a second processor core; performing mutual inter-core checking of the self-test results by using the first processor core to check the second set of self-test results from the second processor core while simultaneously using the second processor core to check the first set of self-test results from the first processor core; and then using the second processor core to immediately execute a recovery mechanism for the first processor core if comparison of the first set of self-test results against reference test results indicates there is a hardware failure at the first processor core.

Runtime software-based self-test with mutual inter-core checking

Certain aspects of the disclosure are directed to methods and apparatuses for health monitoring of wireless connections among vehicles. An example method can include receiving as input to processing circuitry configured and arranged to monitor a health status of wireless communications links between a plurality of vehicles in a vehicle platoon, object information including coordinates of stationary and moving objects, and determining, using the received object information, a relative location of a vehicle among the plurality of vehicles in the vehicle platoon. The method further includes determining, based on the received object information and the relative location of the vehicle, physical parameters for line-of-sight wireless communications between the vehicle and other vehicles in the vehicle platoon. The health status of the wireless communications links can be determined between the plurality of vehicles in the vehicle platoon using the physical parameters for the line-of-sight wireless communications.

Health monitoring of wireless connections among vehicles

A circuit contains a shared memory (), that is used by a plurality of processing elements () that contain cache circuits () for caching data from the shared memory (). The processing elements perform a plurality of cooperating tasks, each task involving caching data from the shared memory () and sending cache message traffic. Consistency between cached data for different tasks is maintained by transmission of cache coherence requests via a communication network. Information from cache coherence requests generated for all of said tasks is buffered. One of the processing elements provides an indication signal indicating a current task stage of at least one of the processing elements. Additional cache message traffic is generated adapted dependent on the indication signal and the buffered information from the cache coherence requests. Thus conditions of cache traffic stress may be created to verify operability of the circuit, or cache message traffic may be delayed to avoid stress.

Circuit and method with cache coherence stress control

Tasks are executed in a multiprocessing system with a master processor core () and a plurality of slave processor cores (). The master processor core (), executes a program that defines a matrix of tasks at respective positions in the matrix and a task dependency pattern applicable to a plurality of the tasks and defined relative to the positions. Each dependency pattern defines relative dependencies for a plurality of positions in the matrix, rather than using individual dependencies for individual positions. In response to the program the master processor core () dynamically stores definitions of current task dependency patterns in a dependency pattern memory. A hardware task scheduler computes the positions of the tasks that are ready for execution at run time from information from information about positions for which tasks have been completed and the task dependency pattern applied relative to those tasks. The tasks that have been computed to be ready for execution are assigned to the slave processor cores ().

Multiprocessor circuit using run-time task scheduling

A multiprocessor system has a background memory and a plurality of processing elements, each comprising a processor core and a cache circuit. The processor cores execute programs of instructions and the cache circuits cache background memory data accessed by the programs. A write back monitor circuit is used to buffer write addresses used for writing data by at least part of the processor cores. The programs contain commands to read the buffered write back addresses from the write back monitor circuit and commands from the programs to invalidate cached data for the write back addresses read by the commands to read the buffered write back addresses. Thus cache management is performed partly by hardware and partly by the program that uses the cache. The processing core may be a VLIW core, in which case instruction slots that are not used by the program can be made useful to include instructions for cache management.

Multiprocessor system with mixed software hardware controlled cache management

Various exemplary embodiments relate to a method and related motion estimation unit for performing motion estimation on video data comprising a plurality of frames. The method may begin by reading a current frame of the plurality of frames from a memory of a motion estimation unit. The method may then select a motion vector for each respective block of pixels in a current row of the current frame. The step of selecting the motion vector may include, for each respective block, selecting, by the motion estimation unit, a candidate vector for at least one block directly surrounding the respective block based on a determination of whether the directly surrounding block has been processed for the current frame, calculating, for each candidate vector, a difference value, and selecting, as the motion vector, the candidate vector with the lowest difference value.

Parallel three-dimensional recursive search (3DRS) meandering algorithm

A circuit arrangement and method of executing program code which utilize power control instructions capable of dynamically controlling power dissipation of multiple hardware resources during execution of a program by a processor. The processor configured to process such power control instructions and to maintain the power modes of the multiple hardware resources to that specified in an earlier-processed power control instruction, such that subsequently-processed instructions will be processed while the power modes of the multiple hardware resources are set to that specified by the earlier-processed power control instruction.

Arrangement and method for controlling power modes of hardware resources

A circuit arrangement and method of controlling power dissipation utilize a register file () with power dissipation control capabilities through a banked register design coupled with enable logic () that is configured to selectively disable unused banks () of registers by selectively gating off clock (), address () and data () inputs supplied thereto.

Register file gating to reduce microprocessor power dissipation

A circuit arrangement, method of executing program code and method of generating program code utilize power control instructions () capable of dynamically controlling power dissipation of multiple hardware resources (-) during execution of a program by a processor (). Moreover, a processor () configured to process such power control instructions () is capable of maintaining the power modes of the multiple hardware resources (-) to that specified in an earlier-processed power control instruction (), such that subsequently-processed instructions (90) will be processed while the power modes of the multiple hardware resources (-) are set to that specified by the earlier-processed power control instruction ().

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Eindhoven, Netherlands

Andrei Sergeevich Terechko