National Semiconductor Corporation

Texas Instruments Corporation

Lumileds LLC

Andrei Papou

Peter J Hopper

Peter Smeys

Peter B Johnson

William David French

Kyuwoon Hwang

Dok Won Lee

Roozbeh Parsa

Ann Gabrys

Wen Yu

Ashish Tandon

Rajat Sharma

Erik William Young

Paul Mawson

Luke Gordon

Steven Hunt

Martin Fallon

Joseph Flemish

Oleg Borisovich Shchekin

Yu-Chen Shen

Anuraag Mohan

Aditi Dutt Chaudhuri

A device may include a metal contact between a first isolation region and a second isolation region on a first surface of an epitaxial layer. The device may include a first sidewall and a second sidewall on a second surface of the epitaxial layer distal to the first isolation region and the second isolation region. The device may include a wavelength converting layer on the epitaxial layer between the first sidewall and the second sidewall.

Monolithic segmented LED array architecture with islanded epitaxial growth

A light-emitting device is disclosed which includes a segmented active layer disposed between a segmented conductivity layer and a continuous conductivity layer, the active layer, the segmented conductivity layer, and the continuous conductivity layer being arranged to define a plurality of pixels, each pixel including a different segment of the segmented conductivity layer and the segmented active layer. A continuous wavelength converting layer disposed on the continuous conductivity layer is provided. A plurality of first contacts, each first contact being electrically connected to a different segment of the segmented conductivity layer is provided. One or more second contacts that are electrically connected to the continuous conductivity layer are also provided, the number of second contacts being less than the number of first contacts.

Monolithic, segmented light emitting diode array

A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to &#x2212;40&#xb0; C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.

Micro-fabricated atomic clock structure and method of forming the atomic clock structure

A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process.

Method of forming a laminated magnetic core with sputter deposited and electroplated layers

Thermally-insulated micro-fabricated atomic clock structure and method of forming the atomic clock structure

An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits

Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants.

MEMS power inductor with magnetic laminations formed in a crack resistant high aspect ratio structure

A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency.

Forming a ferromagnetic alloy core for high frequency micro fabricated inductors and transformers

An inductor is formed on a wafer by attaching a first core structure to the wafer with a pick and place operation, forming a coil with one or more thick metal layers over the first core structure, and then attaching a second core structure to the first core structure with the pick and place operation after the coil has been formed. In addition, the pick and place operation can also be used to attach one or more integrated circuits to the wafer to form an integrated inductive device.

Inductive structure and method of forming the inductive structure with an attached core structure

A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.

Magnetically enhanced power inductor with self-aligned hard axis magnetic core produced in an applied magnetic field using a damascene process sequence

A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.

System and method of galvanic isolation in digital signal transfer integrated circuits utilizing conductivity modulation of semiconductor substrate

The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.

Semiconductor inductor with a serpentine shaped conductive wire interlaced with a serpentine shaped ferromagnetic core

A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.

Method of making a controlled seam laminated magnetic core for high frequency on-chip power inductors

Method of fabricating an inductor structure

The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.

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San Jose, CA, United States of America

Andrei Papou