Intel Corporation

Andrei Ovchinnikov

Andrey Vladimirovich Belogolovy

Ilango S Ganga

Luke L Chang

Evguenii Avramovich Krouk

Andrey Efimov

Evgeny A Kruk

Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.

Techniques to perform forward error correction for an electrical backplane

Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry. The FEC circuitry provides primitives comprising a FEC_UNITDATA.request primitive, a FEC_UNITDATA.signal primitive, and FEC_UNITDATA.indication primitive, the FEC sublayer and includes an encoder having a reverse gearbox and a pseudo-noise generator.

Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Apparatus and systems, as well as methods and articles, encode a data word into an unequal error protection (UEP) codeword and transmit first and second portions of the UEP codeword associated with first and second protection levels across first and second sub-channel subsets associated with first and second error probabilities and a multi-channel communications link, respectively.

Unequal error protection apparatus, systems, and methods

A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bwith a column vector v using common adders to produce a column vector v. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial for a (n, k) Reed-Solomon code. The matrix Bis over GF() including first h columns of a matrix B. A second multiplier unit multiplies non-unity components of a column vector A with non-zero components of the column vector vcomponent-wise in GF(q) to produce a column vector v, q being equal to n+1. A third multiplier unit multiplies diagonal sub-matrices of a matrix C with corresponding components of the column vector vin GF() to produce a column vector v

Fast decoding of Reed-Solomon code

Code shortening techniques are used to achieve a variety of code lengths and code rates for Euclidean geometry low density parity check (EG-LDPC) codes.

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St. Petersburg, Russia

Andrei Ovchinnikov