Apple Inc.

Vmware, Inc.

Sun Microsystems, Inc.

Andrei Dorofeev

John Gregory Dorsey

Bryan R Hinch

Daniel Allen Chimene

Aditya Venkataraman

Cyril De La Cropte De Chanterac

Constantin Pistol

James Michael Magee

Russell Alexader Blaine

Jeremy C Andrus

Nigel R Gamble

Carl Alan Waldspurger

John R Zedlewski

James S Ismail

Evan M Hoke

Gaurav Kapoor

Andrew G Tucker

Varaprasad V Lingutla

Keith Alan Cox

Eric Christopher Saxe

Bart Smaalders

Jonathan Chew

Reza Arastoo

Shirin Dadashi

Mohsen Heidarinejad

Embodiments are presented herein of, inter alia, systems, devices, and associated methods for allocating and distributing power management budgets for classes of tasks being executed by a computer system, based on thermal feedback loops. Specifically, multiple quality-of-service (QoS) tiers may be defined, and each QoS tier may be allocated power based on a different set of thermal feedback loops. QoS tiers including tasks that are invisible to the user may be mitigated more aggressively than QoS tiers including tasks that are visibly supporting user operations.

Quality of service tier thermal control

A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

Adaptive memory performance control by thread group

Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Scheduler for amp architecture with closed loop performance and thermal controller

Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

Scheduler for amp architecture using a closed loop performance and thermal controller

Closed loop performance controller work interval instance propagation

Scheduling of work interval objects in an AMP architecture using a closed loop performance controller

A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.

Performance telemetry aided processing scheme

Scheduler for AMP architecture with closed loop performance controller using static and dynamic thread grouping

An example computer-implemented method includes determining, by an electronic device, that the electronic device has not received a user activity for an interval of time. The method also includes determining, by the electronic device, a contextual state of the electronic device, and adapting, by the electronic device, a sleep delay value based on the determined contextual state of the electronic device. The method also includes determining that the interval of time has exceeded the sleep delay value, and responsive to determining that the interval of time has exceeded the sleep delay value, transitioning, by the electronic device, from a first power state to a second power state, where the first power state is higher or lower than the second power state.

Adaptive sleep delay

Scheduler for AMP architecture with closed loop performance controller

Management of contexts that execute on a computer system is described. More specifically, context scheduling in a virtual machine environment is described. Times at which a context transitions from a scheduled state to a descheduled state and times at which the context transitions from a descheduled state to a scheduled state are recorded for each context. Skew is detected using the recorded times. The amount of skew can be quantified, and a corrective action is triggered if the amount of skew fails to satisfy a threshold value.

Defining and measuring skew between coscheduled contexts

Management of contexts that execute on a computer system is described. More specifically, context scheduling in a virtual machine environment is described. A set of coscheduled contexts is monitored. If a skew metric associated with a first context of the coscheduled contexts fails to satisfy a condition, then a subset of the coscheduled contexts is descheduled although the first context remains scheduled.

Detecting and responding to skew between coscheduled contexts

Management of contexts that execute on a computer system is described. More specifically, context scheduling in a virtual machine environment is described. A set of coscheduled contexts, including at least a first context and a second context, are monitored. The first and second contexts are alternately scheduled and descheduled so that both the first context and the second context are not concurrently scheduled.

Alternating scheduling and descheduling of coscheduled contexts

Growing community of inventors

San Jose, CA, United States of America

Andrei Dorofeev