Infineon Technologies Ag

Infineon Technologies North America Corp.

Andreas Wenzel

Steffen Sonnekalb

Rod G Fleck

Albrecht Mayer

Thomas Kuenemund

Stefan Rueping

Franz Klug

Thomas Kunemund

Eric John Chesters

Stefan Ruping

Boris Reynov

Gary Sheedy

A circuitry is provided. The circuitry comprises a signature memory having stored thereon a plurality of stored signatures. Moreover, the circuitry comprises a signature generator configured to receive one or more monitored signals, and to generate a generated signature depending on at least one of the one or more monitored signals. Furthermore, the circuitry comprises one or more subunits configured to be accessed depending on at least one of the one or more monitored signals. Moreover, the circuitry comprises a protection unit configured to restrict access on the one or more subunits. Furthermore, the circuitry comprises a decision controller configured to compare the generated signature with a stored signature of the plurality of stored signatures to obtain a comparison result. The protection unit is configured to provide access to one of the one or more subunits depending on the comparison result.

Circuitry and method for instruction stream protection

A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode. Moreover, the second processor is configured to determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

System and method for error detection of executed program code employing compressed instruction signatures

According to one embodiment, a data processing arrangement is described comprising a processor configured to carry out a computer program including a plurality of program instructions; a signature determination arrangement configured to determine a signature of the program instructions carried out by the processor wherein the processor is configured to, when it carries out a program instruction of the plurality of program instructions which indicates the next program instruction of the plurality of program instructions to be carried out, provide information about the indication to the signature determination arrangement; wherein the signature determination arrangement is configured to take into account the information in the determination of the signature; and a detector configured to check, when the computer program is completely carried out, whether the determined signature is equal to a reference signature.

Data processing arrangement and method for ensuring the integrity of the execution of a computer program

A processing unit having a control unit configured to execute after a reset phase a sequence of test instructions to detect a manipulation of the processing unit before the control unit decodes a first instruction for a normal operation.

Processing unit that detects manipulations thereof, device comprising two processing units, method for testing a processing unit and a device comprising two processing units

An error detection code (EDC) memory module coupled via a bus to a data memory module. In response to a request for data words from a specified memory address within the data memory module, the data memory module provides a predetermined number of data words and the EDC memory module provides a corresponding EDC word.

Error detection code memory module

Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa.

Device for storing a binary state

A memory arrangement having a memory area with a plurality of memory locations, to which external addresses can be allocated, and an address decoder which is coupled to the memory area and which includes an address input for applying an external address. The address decoder can be switched so that one of the external addresses of an address range is allocated to each memory location of the memory area, or that one of the external addresses of a sub-address range of the address range is allocated to each memory location only within a part-memory area of the memory area. The address decoder is also arranged for identifying the memory location allocated to the external address applied.

Memory device and method for operating a memory device

An integrated circuit having first connections, a first memory cell, first and second prechargers, and first and second data transmission devices. The first connections have a dual-rail signal applied thereto. The first memory cell is connected to the first connections and buffer-stores the dual-rail signal applied to the first connections. The first precharger precharges first lines, which are connected to the first connections. The first data transmission device, which forwards the dual-rail signal stored in the first memory cell to second connections, which are connected to a second memory cell which transmits the dual-rail signal to the first connections again using the second data transmission device. The second precharger precharges second lines, which are connected to the second connections.

Integrated circuit and method for operating the integrated circuit

A semiconductor chip is characterized in that some of the contact points for connecting the semiconductor chip to other components of a system that contains the chip is provided for making a connection with another semiconductor chip that can be mounted onto the first semiconductor chip and that enhances the functions and/or the power of the latter. Such a configuration allows a small semiconductor chip to be produced in a cost-effective manner, using minimal resources and the chip can be enhanced by any number of modules, without modifying the characteristics of the system, in which it is contained.

Semiconductor chip

The present invention relates to electronic packaging and a method for manufacturing the same. According to an embodiment of the present invention, an emulator chip package is designed and assembled such that a bottom portion of the emulator chip package is approximately the same electronic package used to package the target chip. Additionally, a top portion of the emulator chip package is approximately a slightly modified version of the same type of package used to package the target chip. According to an embodiment of the present invention, the top portion of the emulator chip package is attached to the bottom portion of the emulator chip package. The lead connector pins of the top portion of the package preferably leads up, while the connector pins of the bottom portion of the package preferably leads down.

Emulator chip package that plugs directly into the target system

An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.

On-chip debug system

A method and an apparatus for operating a circulating memory that can be addressed by a write pointer and/or a read pointer are disclosed. The method and the apparatus are distinguished by the fact that a jump of the write pointer and/or of the read pointer from the end of the memory to the beginning of the memory and/or vice versa is signaled.

System for operating a circulating memory which can be addressed via a write and/or read pointer by outputting a signal upon an occurrence of a jump of the pointer

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Munich, Germany

Andreas Wenzel