Infineon Technologies Ag

Qimonda Ag

Andreas Täuber

Thomas Hein

Paul Schmölz

Robert Feurle

Aaron Nygren

Jean-Marc Dortu

Ulrich Menczigar

An integrated circuit for receiving data includes an input receiver circuit that is supplied with a data signal and a reference signal. The input receiver circuit converts the data signal into differential input control signals that are supplied to first and second signal paths. The first and second signal paths being connected in parallel. The first signal path includes a first comparator circuit that is connected, via a delay circuit and an amplifier circuit, to an output connection of the integrated circuit. The second signal path includes a second comparator circuit that is likewise connected, via a first inverter circuit and a second inverter circuit, to the output connection of the integrated circuit. The two amplifier circuits act as edge discriminators that drive each other and make it possible to generate, at the output connection, an output signal with the same duty cycle as the data signal without distortion.

Integrated circuit for receiving data

A receiver circuit for receiving and forwarding data signals comprises at least one first and one second input to be used to inject an external digital data signal and a reference signal into the receiver circuit, a multistage input amplifier circuit which comprises a first amplifier stage and a second amplifier stage connected downstream of the first amplifier stage, and a device for actively setting a first operating point of the multistage input amplifier circuit. The multistage input circuit provides the external digital data signal in amplified form at an output and the device generates a bias potential for driving the input multistage amplifier circuit on the basis of the circuit topography of the multistage input amplifier circuit. The bias potential is used to set a second operating point of the first amplifier stage in such a manner that its output signal is within a prescribed third operating point of the second amplifier stage.

Receiver circuit

A method for reading, from a semiconductor memory, data having a data burst length greater than two includes, beginning at a first time, receiving, on an address bus, a first address part associated with memory cells to be addressed. At a second time that is later than the first time, a read command is placed on a command bus to initiate read access to the first memory cells and a second address part associated with memory cells to be addressed is received on the address bus. Beginning at a third time that is later than the second time, data associated with the first and second address parts is transferred to a data bus.

Reading extended data burst from memory

The invention relates to a semiconductor memory apparatus in which the connections of the connecting contacts can be varied. The invention also relates to a semiconductor apparatus which comprises at least two semiconductor memory apparatuses according to the invention.

Semiconductor memory apparatus with variable contact connections, and a corresponding semiconductor apparatus

A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.

Calibration configuration

A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.

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Unterschleissheim, Germany

Andreas Täuber