Infineon Technologies Ag

Andreas T&auml;uber

Robert Feurle

Jean-Marc Dortu

Paul Schm&ouml;lz

Pramod Acharya

Xiaofeng Wu

Aaron Nygren

Michael Pfeiffer

Eckehard Pl&auml;ttner

In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions&mdash;to be performed for a memory access&mdash;from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.

Integrated dynamic memory device and method for operating an integrated dynamic memory

The electrical circuit includes a plurality of circuit components which are connected via a bus. At least one of the circuit components can be tested independently of the other circuit components. The circuit component which is to be tested and the method for testing the circuit component are distinguished in that steps are taken to ensure that, during testing, the circuit component which is tested, outputs no data to the bus, and/or instead of the data which would need to be output to the bus during normal operation, outputs other data to the bus.

Electrical circuit and method for testing a circuit component of the electrical circuit

The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

Integrated memory chip with a dynamic memory

A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

Data output interface, in particular for semiconductor memories

Circuit arrangement for scalable output drivers

The voltage supply provides voltages to an electronic circuit requiring at least two different supply voltages. A plurality of standby supply voltages with different levels are obtained from the highest supply voltage with the aid of a voltage divider.

Standby voltage controller and voltage divider in a configuration for supplying voltages to an electronic circuit

An integrated circuit containing a number of subcircuits is described. Each of the subcircuits contains a driver circuit for driving in each case one controllable voltage source on the basis of a reference value. The driver circuit has a memory unit for storing a reference value and a terminal for outputting a first reference value or for inputting a second reference value. A signal line, which is used for transmitting a signal, is connected to the terminal of the driver circuit of each of the subcircuits. The driving by the driver circuit is effected in each subcircuit on the basis of a common reference value that is transmitted via the signal line. Thus, the time needed for setting the reference values for all subcircuits is relatively short.

Integrated circuit containing a number of subcircuits

An integrated memory is described that has memory blocks with column lines and row lines as well as at least one redundancy row line for replacing in each case one of the row lines in any of the memory blocks. In addition, each memory and memory block has a deactivation unit for deactivating the memory block. The integrated memory has deactivation lines, each of which is connected to an input of the deactivation unit of one of the memory blocks. Each memory block has a deactivation decoder that is connected at the output end to all the deactivation lines. If one of the row lines of a first memory block of the memory blocks is replaced by a redundancy row line of a second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block via the corresponding deactivation line.

Growing community of inventors

Unterschleissheim, Germany

Andreas Täuber

Growing community of inventors

Unterschleissheim, Germany

Andreas T&auml;uber

Andreas Täuber