Qimonda Ag

Infineon Technologies Ag

Andreas Taeuber

Detlev Richter

Luca De Ambroggi

Rainer Spielberg

Rex Kho

Konrad Seidel

Robert Petter

Paul Schmoelz

Marco Ziegelmayer

A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.

Method for classifying memory cells in an integrated circuit

An integrated circuit has a plurality of first memory cells, which are electrically coupled along a first line, and additionally has a plurality of second memory cells which are electrically coupled along a second line. The integrated circuit furthermore has a switching unit having a plurality of switching elements having in turn a first contact and a second contact. The first contact of a first switching element is coupled to the plurality of first memory cells, and the first contact of a second switching element is coupled to the plurality of second memory cells. In addition, the first contact of a third switching element is coupled to the second contact of the first switching element, and the first contact of a fourth switching element is coupled to the second contact of the second switching element.

Integrated circuit with switching unit for memory cell coupling, and method for producing an integrated circuit for memory cell coupling

In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.

Data bus width converter

A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.

Memories, method of storing data in memory and method of determining memory cell sector quality

A device for generating memory-internal command signals from a memory operation command includes a command input for receiving a memory operation command for performing a memory operation in a memory system, a clock signal input for receiving an external clock signal, and an output for applying the memory-internal command signal to a command signal line of the memory system. In the device, the memory-internal command signal is generated at a time which depends on the memory-internal command signal and which is selectively settable and synchronous with a rising or synchronous with a falling edge of the external clock signal.

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Unterschleissheim, Germany

Andreas Taeuber