International Business Machines Corporation

Globalfoundries Inc.

Renesas Electronics Corporation

Andreas Scholze

Chun-chen Yeh

Shogo Mochizuki

Dechao Guo

Edward J Nowak

Brent A Anderson

Robert J Gauthier, Jr

Souvick Mitra

Tom C Lee

Rahul Mishra

You Li

Terence B Hook

Lars W Liebmann

Balasubramanian Pranatharthiharan

Robert Russell Robison

Andrew Herbert Simon

Roger Allan Quon

Myung-Hee Na

A method for forming a device structure provides for forming a fin of a semiconductor material. A first contact is formed on the fin. A second contact is formed on the fin and spaced along a length of the fin from the first contact. A self-aligned gate electrode is formed on the fin that is positioned along the length of the fin between the first contact and the second contact.

Contact-first field-effect transistors

Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage

One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

FINFET having notched fins and method of forming same

Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the structure under the mask, selectively implanting a material through a semiconductor layer and into a buried insulator layer forming an implant region. The implant region is substantially parallel to and below an upper surface of the structure. The method may also include masking an additional portion of the structure; etching a set of access ports though the semiconductor layer and partially through the insulator layer into the implant region; etching at least one tunnel below the upper surface of the structure in the implant region using the set of access; and depositing a conductor into the at least one tunnel and the set of access ports.

Subsurface wires of integrated chip and methods of forming

Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.

Field-isolated bulk FinFET

A method of forming a semiconductor device that includes forming a fin structure, and forming an undoped epitaxial semiconductor material on the fin structure. A first portion of undoped epitaxial semiconductor material is formed on the sidewall of at least one of a source region portion and a drain region portion of the fin structure. A second portion of the undoped epitaxial semiconductor material is formed on the recessed surface of a bulk semiconductor substrate that is present at the base of the fin structure. The method further includes forming a doped epitaxial semiconductor material on the undoped epitaxial semiconductor material. The undoped epitaxial semiconductor material and the doped epitaxial semiconductor material provide a source region and drain region.

A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions.

Growing community of inventors

Colchester, VT, United States of America

Andreas Scholze