Cypress Semiconductor Corporation

Andreas Scade

Stefan Guenther

Jaskarn Singh Johal

David W Still

Jeong-Mo Hwang

Jay Ashokkumar

James Allen

A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Current controlled recall schema

A memory circuit includes a high voltage region providing storage of a nonvolatile bit, and a low voltage region providing at least partial storage of a volatile bit. The high and low voltage regions are isolated from one another and formed by a plurality of transistors in series between a current source and a bit line.

5T high density nvDRAM cell

A process of operating a memory array includes performing all volatile and nonvolatile operations on an nvDRAM cell array via a single data interface and using only DRAM-level signals on the data interface.

Architecture of a nvDRAM array and its sense regime

A memory circuit includes a single transistor storing both volatile and nonvolatile bit charges.

3T high density nvDRAM cell

5T high density NVDRAM cell

A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.

Read and volatile NV standby disturb

A memory cell array includes reference cells each associated with a plurality of data cells of the array.

Dummy cell for memory circuits

A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.

Growing community of inventors

Dresden, Germany

Andreas Scade