Microchip Technology Inc.

Andreas Reiter

Yong Yuenyongsgool

Stephen Bowling

Bryan Kris

Alex Dumais

Jason Michael Sachs

Michael I Catherwood

David Mickey

Calum Wilkie

Justin Oshea

Joseph Harry Julicher

Sean Steedman

Tim Phoenix

John Day

Sankar Rangarajan

Frank Ziegenhorn

Anton Alkhimenok

Tibor Futo

Lucio Di Jasio

Franz Thalheimer

Carlo Lombardi

Sean Stacy Steedman

An apparatus includes a pulsed-width modulation (PWM) generator circuit to generate generally complementary PWM signals. The signals are to prevent two complementary switches that receive the complementary PWM signals from both being activated at a same time. The PWM signals are generally complementary with respect to their active portions. The apparatus includes an override circuit to override at least one of the complementary PWM signals to yield adjusted PWM signals. The adjusted PWM signals are to cause the two complementary switches to be activated at a same time when the adjusted PWM signals are received at the two complementary switches.

Override mechanism for PWM operation

A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.

Device and methods for functional descriptor-based DMA controller

A system and method is provided including a first pulse width modulation (PWM) generator circuit including a first timer to generate a first cycle count, a first configuration register to define characteristics of a first electrical pulse to be generated, and a trigger cycle count specifying a timing of a first trigger signal, and a first load enable input to load a new configuration value into the first configuration register, a second PWM generator circuit including a second timer to generate a second cycle count, a second configuration register to define characteristics of a second electrical pulse to be generated, a second load enable input to load a new configuration value into the second configuration register, and a load enable selector to selectively drive the second load enable input based on the first trigger signal.

System and method for configuring coordinated PWM generators

A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.

Programmable fault violation filter

A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register contents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents.

System and methods for ramp control

An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

Central processing unit with enhanced instruction set

Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit

A light emitting diode (LED) running light comprises a current sink and a plurality of series coupled LED block cells; each of the plurality of LED block cells comprising a LED and a bypass circuit to the current sink, wherein each series coupled LED sequentially turns on (lights) when a voltage source increases by additive voltage increments of at least the turn-on voltage of each LED in the series coupled string until all LEDs are on (lit). The current sink maintains a desired current value through the LEDs and may also be used to provide waveforms for diagnostic and timing purposes.

Apparatus and method for LED running light control and status

In a pulse width modulation light emitting diode (LED) controller an error amplifier and output load switch are synchronously controlled to prevent service life shortening current overshoot through the LEDs and slowing discharging currents causing color temperature shifting in the light output from the LEDs. A plurality of switching arrangements for the error amplifier and the compensation network may be provided in a single integrated circuit LED dimming controller, and outputs for controlling a variety of differently configured output power switch combinations for disconnecting or shorting the LEDs, or disconnecting the output capacitor during off times of the modulated dimming control signal.

Method and system for improving LED lifetime and color quality in dimming apparatus

A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to-analog converter (PDM DAC) having a selectable response mode low pass filter.

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Feldkirchen-Westerham, Germany

Andreas Reiter