Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.

Other

Technische Unversität Berlin

Pac Tech - Packaging Technologies Gmbh

Technische Universitaet Berlin

Andreas Ostmann

Elke Zakel

Rolf Aschenbrenner

Paul Kasulke

Lothar Dietrich

Dionysios Manessis

Ivan Ndip

Frank Ansorge

Lars Böttcher

Thomas Löher

Manuel Seckel

Rainer Patzelt

Ghassem Azdasht

Tanja Braun

Ralf Schmidt

Jorg Gwiasda

Karl-Friedrich Becker

Erik Jung

Gerald Motulla

Mathias Koch

Stefan Karaszkiewicz

David Lin

Alexander Neumann

Harald PÖTTER

What is disclosed is a module arrangement. An antenna device and at least one electronic component are arranged next to each other and within one plane between a top side and a bottom side of the module arrangement. A shielding device which has a shielding effect relative to electromagnetic signals is located between the antenna device and the electronic component. Additionally, a method for manufacturing a module arrangement is disclosed.

Module arrangement comprising an integrated antenna and embedded components and method for manufacturing a module arrangement

What is disclosed is a module arrangement having an antenna layer, a shielding layer, a distribution layer and a component layer. The antenna layer supports an integrated antenna device. The shielding layer has a shielding effect relative to electromagnetic signals. The distribution layer has structures for distributing signals and/or electrical energy. Finally, the component layer supports embedded electronic components. In addition, a device comprising module arrangements and a method for manufacturing a module arrangement are disclosed.

Module arrangement comprising embedded components and an integrated antenna, device comprising module arrangements, and method for manufacturing

The invention relates to a device and method for producing targeted flow and current density patterns in a chemical and/or electrolytic surface treatment. The device comprises a flow distributor body which is disposed, with the front face thereof, plane-parallel to a substrate to be processed, and which has outlet openings on the front face, through which process solution flows onto the substrate surface. The process solution flowing back from the substrate is led off through connecting passages onto the rear face of the flow distributor body. At the same time a targeted distribution of an electrical field on a conductive substrate surface is effected by a specific arrangement of said connecting passages.

Device and method for producing targeted flow and current density patterns in a chemical and/or electrolytic surface treatment

An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.

Electronic assembly including an embedded electronic component

The invention relates to a method for generating an electronic system for application to freeform surfaces, a method for producing freeform surfaces having an electronic system, and an electronic system and a combination of a freeform surface having at least one such system. According to the invention, an elastic interconnect device having an elastic substrate and an elastic, fanned-out contact structure with contact surfaces comprised of conductor lines is generated first. Then, electronic components are mounted on the interconnect device. Finally, the interconnect device is encapsulated. If a freeform surface with an electronic system is to be generated, the electronic system produced in this way is then mounted on the previously provided freeform surface.

Method for generating an electronic system, method for generating a freeform surface having such a system, and electronic system and freeform surfaces having such a system

The present invention relates to a method for the production of an expandable circuit carrier in which a starting material for an expandable substrate is applied on an electrically conductive foil which forms an expandable substrate layer which is connected to the foil, after which the foil is structured such that it forms a conductor structure having at least one expandable strip conductor. The present invention further relates to an expandable circuit carrier which can be produced by the method.

Expandable circuit carrier

A method is provided for making an electrical connection with a microelectronic component arranged on or embedded within a surface of a circuit board layer or a substrate. The microelectronic component has an electrical contact face that is accessible on a surface of the microelectronic component. An electrically conducting bump is applied to the electrical contact face of the microelectronic component. A metal foil or metal coat is applied via a coating of an insulating binder to the surface of the circuit board under an action of pressure and/or heat so that the electrically conducting bump penetrates the coating of the insulating binder to make the electrical connection between the metal foil or metal coat and the electrical contact face.

Method for electrically connecting to a contact of a microelectronic component on a circuit board or substrate

A method for producing encapsulated chips includes preparing a wafer with contacts projecting from a surface of the wafer. The wafer is disposed on a dicing substrate and diced into a plurality of spaced chips on the dicing substrate. The contacts are covered with a protection arrangement, then injection molding being conducted to introduce encapsulation material into the contacts and the trenches. Then the protection arrangement is removed so that the contacts are exposed.

Method for producing encapsulated chips

The present invention relates to a method of forming a structured metallization on a semiconductor wafer, wherein a main surface of the wafer has a passivation layer applied thereto, which is structured so as to determine at least one bond pad. Initially, a metal bump is produced on the at least one bond pad. An activated dielectric is then produced on the areas of the passivation layer on which the structured metallization is to be formed. Finally, metal is chemically deposited directly on the activated dielectric and on the metal bump in such a way that the structured metallization formed on the activated dielectric and the metal chemically deposited on the metal bump are electro-conductively joined.

Method for forming a structured metallization on a semiconductor wafer

Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (,), in conjunction with which, by means of a solder-deposit carrier (,) which is provided with a structured, electrically conductive coating (,) with bond pads (,) for the arranging of solder deposits (,) and their transfer to correspondingly arranged bond pads (,) of a substrate (,), an electrical check of the wiring structure of the substrate (,) takes place during the transfer of the solder deposits (,).

Method and apparatus for testing chips

Method for the preparation of electrodeposited or galvanically deposited bumps for the bonding of integrated circuits, characterized by two subsequent metal depositions, deposited without an external current source (chemical metal deposition) on a metallization 1, the first deposition being thicker than the second and the second deposition being more even or more regular throughout a large area than the first one.

Growing community of inventors

Berlin, Germany

Andreas Ostmann