Infineon Technologies Ag

Qimonda Ag

Andreas Orth

Thomas Hecht

Albert Birner

Matthias Goldbach

Jörn Lützen

Stephan Kudelka

Dirk Manger

Peter Moll

Stefan Jakschik

Michael Stadtmueller

Peter Lahnor

Uwe Schröder

Matthias Foerster

Ulrich Mantz

Lars Heineck

Odo Wunnicke

Johannes Heitmann

A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes

The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer behavior of the semiconductor wafer which is brought about by the buried structure when the semiconductor wafer is irradiated with electromagnetic radiation in the infrared range and arises as a result of the significantly longer wavelengths of the radiation used in comparison with the lateral dimensions of the buried structure is utilized to determine the depth of the buried structure by spectrometric and/or ellipsometric methods.

Method for determining the depth of a buried structure

The invention provides a method for fabricating a memory cell, a substrate () being provided, a trench-type depression () being etched into the substrate (), a barrier layer () being deposited non-conformally in the trench-type depression (), grain elements () being grown on the inner areas of the trench-type depression (), a dielectric layer () being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements () growing selectively on the inner areas () of the trench-type depression () in an electrode region () forming a lower region of the trench-type depression () and an amorphous silicon layer continuing to grow in a collar region () forming an upper region of the trench-type depression ().

Memory cell and method for fabricating it

In a method for fabricating trench capacitors, in particular for memory cells having at least one selection transistor for integrated semiconductor memories, a trench for the trench capacitor is formed. The trench has a lower trench region, in which the capacitor is disposed, and an upper trench region, in which an electrically conductive connection from an electrode of the capacitor to a diffusion zone of the selection transistor is disposed. The method reduces the number of process steps for the fabrication of memory cells and enables fabrication of buried collars in the storage capacitors with an insulation quality as required for the fabrication of very large-scale integrated memory cells (&#x3c;300 nm trench diameter).

Method for fabricating trench capacitors for integrated semiconductor memories

A method for fabricating a semiconductor trench structure includes forming a trench in a semiconductor substrate and filling it with a filler. A first thermal process having a first maximum temperature cures the filler. Removing the filler from an upper region of the trench as far as a boundary surface defines a collar region. In a second thermal process having a second maximum temperature that is not significantly higher than the first maximum temperature, a liner is deposited on the collar region and the boundary surface. The liner is removed from the boundary surface, thereby exposing the filler. The filler is then removed from a lower region of the trench.

Semiconductor trench structure

Growing community of inventors

Dresden, Germany

Andreas Orth