Infineon Technologies Ag

Andreas Martin

Andrea Mitchell

Karl-Henrik Rydén

Uwe Hodel

Jochen Von Hagen

Wilhelm Asam

Josef Fazekas

David Smeets

Daniel Beckmeier

Wolfgang Heinrigs

Alfred Schuetz

Gunnar Zimmermann

A method for the computer-aided characterization of a circuit comprising a semiconductor layer and a semiconductor component region embedded in the semiconductor layer in an electrically insulated manner, wherein the semiconductor component region is optionally coupled to a dielectric layer structure to be protected, the method comprising determining an indication representing vis-&#xe0;-vis the semiconductor layer an intensity of an electrical charging of the semiconductor component region by a production process used to produce the circuit, wherein a physical construction of the semiconductor component region is taken into account when determining the indication, and classifying the semiconductor component region taking account of the indication.

Method, and storage medium and also device for carrying out same

A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.

Semiconductor devices and methods for testing a gate insulation of a transistor structure

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction.

Methods of manufacturing semiconductor devices

Semiconductor devices having transistors along different orientations

In one embodiment, a method of forming a semiconductor device includes forming a well region within a substrate. A plurality of transistors is formed within and/or over the well region. The method further includes forming a first discharge device within the substrate. The first discharge device is coupled to the well region and a low voltage node. During subsequent processing, the first discharge device discharges charge from the well region.

Semiconductor discharge devices and methods of formation thereof

A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line.

Dielectric film and layer testing

The invention relates to a device and a method for detecting the reliability of integrated semiconductor components. The device includes a carrier substrate for receiving an integrated semiconductor component that will be examined, a heating element, and a temperature sensor. The temperature sensor has at least a portion of a parasitic functional element of the semiconductor component. As a result, reliability tests can be carried out in a particularly accurate and space-saving manner.

Growing community of inventors

Munich, Germany

Andreas Martin