Infineon Technologies Ag

Qimonda Flash Gmbh

Qimonda Ag

Qimonda Flash Gmbh & Co. Kg

Andreas Kux

Detlev Richter

Herbert Palm

Michael Smola

Josef Willer

Ronald Kakoschke

Girolamo Gallo

Konrad Seidel

Uwe Augustin

Gert Koebernick

Regina Stokan

Gunther Plasa

Ramirez Xavier Veredas

Volker Zipprich-Rasch

Roberto Ravasio

Mirko Reissmann

Daniel-André Löhr

Sören Irmer

Eric-Roger Brücklmeier

Juergen Engelhardt

Helga Braun

Sudhindra Prasad

Gert Köbernik

Hans Heitzer

In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

Memory device and method providing logic connections for data transfer

Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation.

Integrated circuit and method to operate an integrated circuit

Embodiments of the present invention relate to a method to operate an integrated circuit that includes a memory. The memory encompasses a first and a second threshold level. The invention further relates to integrated circuits including a memory with a first and a second threshold level and a method to determine an operating point of an integrated circuit.

Method of operating an integrated circuit, integrated circuit and method to determine an operating point

Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state.

Method of operating an integrated circuit having at least one memory cell

In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

Integrated circuits, memory controller, and memory modules

A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

Memory device with adaptive sense unit and method of reading a cell array

A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.

Memory device and method for verifying information stored in memory cells

An individual configuration contains at least a first structure and a second structure, which are aligned with respect to each other. A position sensing device that senses a relative position of the first structure with respect to the second structure, in order to establish that a manipulation has been performed on the configuration, is provided.

Individual configuration

The access time for the use of an electronic device, for example a chip, is prolonged after each unauthorized access attempt. The access time is determined by the time for the matching of the turn-on voltages of two floating gate cells. Before an access attempt, the turn-on voltage of one cell is set to a predefined initial value and the turn-on voltage of the other cell is set to a value which is higher in comparison and which is increased after each unauthorized access.

Circuit and method for protecting electronic devices

A method for securing a multi-dimensionally constructed chip stack, which has a plurality of part chips which are interconnected at respective contact areas and of which at least one contains functional components, includes the steps of providing respective conductor tracks in the part chips and providing feed-through contacts at the respective contact areas, which in each case interconnect conductor tracks of various part chips so that a continuous electrical signal path running through the part chips is formed. An electrical signal is transmitted from a transmitting device provided at a first end of the electrical signal path to a receiving device provided at a second end of the electrical signal path. When the electrical signal cannot be received, it is determined that the chip stack has been damaged. A device for securing a chip stack and a chip configuration are also provided.

Method and device for securing a multi-dimensionally constructed chip stack and chip configuration

A method for fabricating a wiring which runs at least piecewise in a substrate. At least one conductive connection runs in the semiconductor substrate and at least one conductive connection runs on the semiconductor substrate being provided. The semiconductor component enables applications in which high security against external manipulations is important.

Method for fabricating a semiconductor component having a wiring which runs piecewise in the substrate, and also a semiconductor component which can be fabricated by this method

A semiconductor configuration includes at least one semiconductor chip having a first chip side, a second chip side, and connections passing through the at least one semiconductor chip, active structures on the first chip side and the second chip side, the connections electrically connecting the active structures to one another, a support having a first support side, a second support side, plated-through holes, and non-conducting regions running alternately with regular spacings from the first support side to the second support side, the plated-through holes spaced apart from one another to define a hole spacing distance between the holes, contact connections connecting the second chip side to the first support side, the contact connections spaced apart from one another to define a connection spacing distance between the contact connections, and the hole spacing distance being smaller than the connection spacing distance.

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Haar, Germany

Andreas Kux