Globalfoundries Inc.

Advanced Micro Devices Corporation

Andreas Kurz

Jens Poppe

Roman Boschke

Christoph Schwan

Jan Hoentschel

Andy C Wei

Andrei Sidelnicov

Thilo Scheiper

Stephan Kronholz

James F Buller

Uwe Griebenow

Maciej Wiatr

Matthias Kessler

Oliver Aubel

Alexandru Romanescu

John Morgan

Sven Beyer

Peter Javorka

Ricardo Pablo Mikalo

Klaus Hempel

Kaveri Mathur

Roland Stejskal

Sergej Mutas

Clemens Wündisch

Christian Hennesthal

Holger Pagel

A semiconductor device with a semiconductor-on-insulator (SOI) structure is provided including an insulating layer and a semiconductor layer formed on the insulating layer and a fuse. The fuse includes a first at least partially silicided raised semiconductor region with a first silicided portion and, adjacent to the first at least partially silicided raised semiconductor region, a second at least partially silicided raised semiconductor region with a second silicided portion. The second silicided portion is formed in direct physical contact with the first silicided portion.

Raised e-fuse

A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.

A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.

Semiconductor device comprising an e-fuse and a FET

Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and second pre-heating lines positioned generally parallel to and co-planar with the fuse part, and electrically connected with the fuse part. The electronic fuse structure also includes a cathode physically and electrically connected to the first pre-heating line and an anode physically and electrically connected to the second pre-heating line.

Integrated circuits with electronic fuse structures

In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.

Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing heat generation

Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-&#x3ba;/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-&#x3ba; dielectric layer on the STI region, forming a metal gate on the high-&#x3ba; dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.

Semiconductor fuse with enhanced post-programming resistance

A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure.

Semiconductor device fabrication methods

An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.

Semiconductor device comprising a buried poly resistor

An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

BEOL anti-fuse structures for gate last semiconductor devices

Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Semiconductor device comprising metal-based eFuses of enhanced programming efficiency by enhancing metal agglomeration and/or voiding

In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

SOI device with a buried insulating material having increased etch resistivity

Disclosed herein is a metal e-fuse device that employs an intermetallic compound programming mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.

Metal e-fuse with intermetallic compound programming mechanism and methods of making same

A semiconductor-based electronic fuse may be provided in a sophisticated semiconductor device having a bulk configuration by appropriately embedding the electronic fuse into a semiconductor material of reduced heat conductivity. For example, a silicon/germanium fuse region may be provided in the silicon base material. Consequently, sophisticated gate electrode structures may be formed on the basis of replacement gate approaches on bulk devices substantially without affecting the electronic characteristics of the electronic fuses.

Methods of forming efuse devices

In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.

Growing community of inventors

Dresden, Germany

Andreas Kurz