Cadence Design Systems, Inc.

Synopsys, Inc.

International Business Machines Corporation

Other

Andreas Kuehlmann

Philip Chong

Christoph Albrecht

Ellen Sentovich

Marat Boshernitsan

Roberto Passerone

Xiaoqun Du

Scott McPeak

Viresh Paruthi

Geert Janssen

Andy Chou

Kenneth L McMillan

Florian Karl Krohm

Shmuel Sagiv

Roger H Scott

Kit Transue

Tobias Welp

Jason Raymond Baumgartner

Louise Helen Trevillyan

Sandip Kundu

Kaushik Ravindran

Arvind Srinivasan

Sascha Richter

David John Seibert

Nathan Kitchen

Malay Kumar Ganai

A method to emulate a system represented by one or more of hardware portions and software portions is described. The method comprises determining whether a subset of the one or more hardware portions and software portions have been tested, and identifying whether the system has performed to a specification based on the testing. The method further comprising, when the system has not performed to the specification, determining one or more of the hardware and software portions to update for retesting.

Software and hardware emulation system

A method is provided to evaluate impact of a change to code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.

Static analysis of computer code to determine impact of change to a code component upon a dependent code component

A method is provided to prioritize testing of computer program code comprising: determining first test coverages of items within a first source code version for multiple tests; storing in a non-transitory storage device, a first history that indicates the determined first test coverages of the items within the first source code version; identifying occurrences of the items within a second source code version; determining first weights associated with tests, wherein a respective weight associated with a respective test is indicative of a respective number of respective items within the second source code version that are covered by the respective associated test according to the first history; and prioritizing the multiple respective tests based at least in part upon the determined first weights.

Prioritization of tests of computer program code

A method is provided to evaluate tests of computer program code comprising: configuring a computer to produce, in a computer readable storage device, a code filter to indicate one or more respective portions of the computer program code to respectively either omit from or to include in a determination of adequacy of results; and comparing test results with the computer program code with the one or more respective portions filtered using the code filter to respectively either omit the respective portions from or include the respective portions in the determination as indicated by the code filter.

Policy evaluation based upon dynamic observation, static analysis and code change history

A method is provided to evaluate impact of a change in code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.

In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.

General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software

Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software

A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.

Optimizing integrated circuit design through use of sequential timing information

Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.

Temporal decomposition for design and verification

Reducing critical cycle delay in an integrated circuit design through use of sequential slack

A method and apparatus for producing a verification of digital circuits is provided. In an exemplary embodiment, a set of Boolean and Integer constraints are derived, and a set of Boolean and Integer stimuli are generated that meet the constraints. These stimuli are then used to verify a digital design, and a verification report is generated. In other example embodiments, a computing apparatus and computer software product are provided. The computer software product containing a set of executable instructions that, when executed, configure the computing apparatus to produce a verification report by the provided methods.

System, methods and apparatus for generation of simulation stimulus

Growing community of inventors

Berkeley, CA, United States of America

Andreas Kuehlmann