International Business Machines Corporation

Globalfoundries Inc.

Andreas Koenig

Cedric Lichtenau

Tilman Gloekler

Bishop Chapman Brock

Sascha Junghans

Preetham M Lobo

Rolf Fritz

Santosh Balasubramanian

Pradeep N Chatnahalli

William Eric Hall

Peter Anthony Sandon

Thomas Pflueger

Elaine Rivette Palmer

Todd Alan Venton

Daniel D Sentler

Manfred Walz

Jens Kuenzer

Gerd Konrad Bayer

John Farrugia

Christopher S Smith

Carl Mayer

Markus Cebulla

Joerg Behrend

Jeshua Daniel Smith

Onur Keles

Felix Eickhoff

Frank Koeble

The invention relates to an electronic circuit () having one or more latch scan chains (), the electronic circuit () comprising (i) a built-in test structure (); (ii) generation means () for simultaneously generating scan-in data for each of said scan chains (); (iii) interception means () for simultaneously intercepting test lines () of said scan chains (), said test lines () comprising scan-in lines () and/or control lines (). Said interception means () are responsive to said generation means () in order to simultaneously feed the generated scan-in data into each of said scan chains () for initializing the electronic circuit (). The invention further relates to a method for initializing an electronic circuit (), as well as a data processing system () for initializing an electronic circuit ().

Electronic circuit having serial latch scan chains

Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

First-in-first-out buffer

A protection circuit can be used with a computer system having a master device and at least one slave device that are connected by an inter-integrated circuit (I2C) bus. A first access request is received that includes an address that identifies a first slave device. In response to a permissible mode, the first access request is communicated to the first slave device using the I2C bus. A sticky protection bit can be set. In response to the sticky protection bit being set, the protection circuit can be placed in a protected mode. A second access request is received. The second access request can be determined to be a protected access to the first slave device. In response to the determining and the protected mode, the second access request to the first slave device can be denied.

Data access protection for computer systems

Secure extraction of state information of a computer system is provided. A method includes obtaining, by a security engine of a system, a public encryption key associated with a private decryption key; generating an extraction key that is inaccessible outside of the security engine; encrypting the extraction key with the public encryption key, to thereby obtain an encrypted extraction key; collecting state information of the system; encrypting the collected state information with the extraction key and storing the encrypted collected state information; and based on a request for access to the stored encrypted collected state information by a request for the extraction key, providing the extraction key to facilitate decryption of the stored encrypted state information.

Confidential extraction of system internal data

Embodiments include receiving, at a microcontroller of a chip, a request to execute a first task having a first priority. Embodiments further include determining that a second task having a second priority is currently executing. Embodiments further include determining that the first priority is higher than the second priority. Embodiments further include determining whether a value in a register indicates that the second task can be interrupted. If it is determined that the second task can be interrupted, embodiments further include triggering execution of the second task. If it is determined that the second task cannot be interrupted, embodiments further include waiting for lapse of a time period since receipt of the request to execute the first task, and interrupting the second task upon detecting lapse of the time period, or detecting, prior to the lapse of the time period, that the second task can be interrupted.

Interruption of chip component managing tasks

Embodiments include an apparatus comprising a processor and a computer readable storage medium having computer usable program code. The computer usable program code can be configured to determine whether priority of a requested task is higher than a priority of a currently executing task. The computer usable program code can be further configured to determine whether a value indicates that the currently executing task can be interrupted. The computer usable program code can be configured to trigger execution of the requested task on the processor, if the value indicates that the currently executed task can be interrupted. The computer usable program code can be further configured to wait for lapse of a time period and, interrupt the currently executing task upon detection of lapse of the time period or detection of a change to the value, if the value indicates that the currently executing task cannot be interrupted.

A system and a method for simulation using multiple programming languages is provided. The method can include receiving an annotated source having a first plurality of instructions written in a first programming language and receiving an annotation having a second plurality of instructions written in a second programming language and associated with an annotated instruction from the first plurality of instructions. The method can include extracting the second plurality of instructions to create a routine from the annotation. The method can include building a shared library that contains the routine. The method can include building an application object file by assigning an address to each instruction of the first plurality instructions. The method can include creating an annotation table that contains an address for the annotated instruction and an associated symbol.

Management of mixed programming languages for a simulation environment

A computer program product for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Computer program product for handling communication link problems between a first communication means and a second communication means

A method for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Method, device, computer program product and data processing program for handling communication link problems between a first communication means and a second communication means

Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

Method and system for generating an integrated circuit chip facility waveform from a series of chip snapshots

An improved method for connection exploration in a network is disclosed, wherein said network includes a plurality of network elements each including at least one port, wherein a globally unique identifier is assigned to each individual port of said network elements, and wherein connected ports of two network elements transfer their globally unique identifiers over a corresponding connection using heartbeat-ordered sequences. The method comprises capturing said transferred globally unique identifiers at receiving ports, storing each of said captured globally unique identifiers at a corresponding receiving port, reading out said transferred globally unique identifiers stored at each port of said network elements using an in-band access, matching said read out globally unique identifiers to a hardware configuration data set to identify connected network elements and connections between said connected network elements, and recording information about existing connections between said network elements.

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Boeblingen, Germany

Andreas Koenig