Continental Teves, Ag and Company Ohg

Freescale Semiconductor,inc.

Continental Ab & Co. Ohg

Andreas Kirschbaum

Adrian Traskov

Wolfgang Fey

Mario Engelmann

Micha Heinz

Anthony M Reipold

Frank Michel

Lukusa Didier Kabulepa

Houman Amjadi

Luc Van Dijk

Anthony Reipold

A microprocessor system () for controlling or regulating at least partly safety-critical processes, comprising two central processing units () integrated in a chip housing, a first and a second bus system, at least one full memory () on the first bus system, at least one test data store () on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory () on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator () is arranged at least on the second bus system, in which case at least part of the full memory on the first bus is additionally backed up using another test data store () and test data on the first bus. The invention further relates to the use of the above microprocessor system in motor vehicle controllers.

Microprocessor system for controlling or regulating at least partly safety-critical processes

An integrated circuit arrangement on a common chip or chip support, for safety critical applications, in particular for use in control and regulation units for a motor vehicle braking system, including at least one microprocessor system module, which has at least one core processor, provided with at least one ROM and at least one RAM, at least one power module for controlling external users and at least one monitoring module for monitoring at least parts and/or part systems of the circuit arrangement, the circuit arrangement including at least one temperature sensor for recording a chip temperature.

Integrated circuit arrangement for safety critical regulation systems

A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product

The invention relates to a microprocessor system () for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units () integrated into a chip housing, a first and a second bus system, at least one complete memory () on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Microprocessor system for controlling at least partly safety-critical processes

An automated method for producing integrated circuit arrangements for automotive vehicle control systems provides at least two logically isolated subsystems () and, in addition to the logical isolation, effects a spatial (physical) isolation of the subsystems on the surface available on the circuit arrangement.

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Darmstadt, Germany

Andreas Kirschbaum