Globalfoundries Inc.

International Business Machines Corporation

Advanced Micro Devices Corporation

Andreas Kerber

William McMahon

Suresh Uppal

Tanya Nigam

Eduard Albert Cartier

Michael Patrick Chudzik

Siddarth A Krishnan

Naim Moumen

Kingsuk Maitra

Fernando Jose Guarin

Salvatore Cimino

Dieter Lipp

Hao Jiang

Marc Herden

CMOS switching devices are connected to testing equipment that applies AC to stress the CMOS switching devices. The testing equipment varies rise and fall times of drain and gate voltages, and varies offsets of the drain and gate voltages of the CMOS switching devices. The amount of hot carrier injection (HCI) within the CMOS switching devices is measured when the rise and fall times of the drain and gate voltages cross over, to establish AC HCI contribution to device degradation of the CMOS switching devices. Further, these methods can correlate the AC HCI contribution of the CMOS switching devices to CMOS logic devices based on ring oscillator (RO) degradation of ROs similarly tested or simulated, to produce AC HCI contribution for the CMOS logic devices.

Assessment of HCI in logic circuits based on AC stress in discrete FETs

At least one method and system involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

Methods, apparatus and system for screening process splits for technology development

At least one method and system disclosed herein involves performing a time-dependent dielectric breakdown (TDDB) test and a bias temperature instability (BTI) test on a device. A device having at least one transistor and at least one dielectric layer is provided. A test signal is provided for performing a TDDB test and a BTI test on the device. The TDDB test and the BTI test are performed substantially simultaneously on the device based upon the test signal. The data relating to a breakdown of the dielectric layer and at least one characteristic of the transistor based upon the TDDB test and the BTI test is acquired, stored, and/or transmitted.

At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.

Methods, apparatus and system for voltage ramp testing

At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Gate dielectric protection for transistors

Methods are provided for operating a memory device. An exemplary method involves obtaining a standby current through a memory block and adjusting a supply voltage for the memory block based on the obtained standby current. An exemplary memory device includes a block of one or more memory cells, a voltage regulating element coupled to the block to provide a supply voltage to the block, a current sensing element coupled to the block to measure current through the block, and a control module coupled to the voltage regulating element and the current sensing element to adjust the supply voltage provided by the voltage regulating element based on a measured current through the block obtained from the current sensing element.

Devices having bias temperature instability compensation

A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.

Techniques for the fabrication of thick gate dielectric

A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.

Integrated circuit decoupling capacitor arrangement

A semiconductor circuit is provided that includes a short channel device, and a long channel device that is electrically isolated from the short channel device. The long channel device comprises a plurality of first gate electrodes, a first source region adjacent one of the plurality of first gate electrodes, a first drain region adjacent another of the plurality of first gate electrodes, and a plurality of common source/drain regions positioned between adjacent ones of the plurality of first gate electrodes. The first gate electrodes each overlie portions of a layer of high-dielectric constant (k) gate insulator material. Each of the first gate electrodes are electrically coupled to at least one of the other first gate electrodes.

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Mount Kisco, NY, United States of America

Andreas Kerber