Intel Corporation

Andreas Jörn Leistner

Georgios Yorgos Palaskas

Andreas Roithmeier

Thomas Gustedt

Svetozar Broussev

Various designs for MOS transistor-based RF switch topologies for high speed capacitive tuning of oscillators switch circuits include a main switch device comprising a gate connected to a control terminal, a drain connected to a first terminal that is connected to the first capacitor, and a source connected to a second terminal that is connected to the second capacitor. The switch further comprises a first NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the first terminal. The switch further comprises a second NMOS device having a gate connected to the main switch device gate, a source connected to a ground, and a drain connected to the second terminal. The switch further comprises a pair of PMOS devices each having drains connected respectively to the first and second terminals.

MOS transistor-based RF switch topologies for high speed capacitive tuning of oscillators

Apparatus and methods for disrupting or preventing periodicity in DTC circuits are provided. In an example, a communication circuit can include a digital-to-time converter (DTC) and a processing path coupled to the DTC. The DTC can be configured to receive reference information, modulation information and first dither information, and to provide a modulated signal using the reference information, the modulation information and the first dither information. The processing path can be configured to receive second dither information and to cancel the first dither information using the second dither information, wherein the DTC is configured to disrupt processing periodicity of the communication circuit using the first dither information.

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Grasbrunn, Germany

Andreas Jörn Leistner