Nxp B.v.

Nxp Usa, Inc.

Andreas Johannes Köllmann

Ulrich Moehlmann

Cristian Pavao Moreira

Steffen Rode

Bernard Burdiek

Joachim Utzig

Christian Scherner

Joerg Syré

A system includes a phase-shift to duty-cycle converter and a low pass filter. The phase-shift to duty-cycle converter has a first input for a reference clock and a second input for a phase-shifted clock that is phase-shifted relative to the reference clock. The low pass filter has an input coupled to an output of the phase-shift to duty-cycle converter and an output for an output signal. In some implementations, the phase-shift to duty-cycle converter includes a simple logic gate and a reset-set flip flop. The simple logic gate has a third input coupled to the first input and a fourth input coupled to the second input, and the reset-set flip flop has a fifth input coupled to the first input and a sixth input coupled to the second input. The low pass filter is coupled to the output of one of the simple logic gate and the reset-set flip flop.

Analog phase selection test system

Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module. Example embodiments include a radar system () comprising a plurality of radar transceiver modules () mounted to a common PCB (), the plurality of radar transceiver modules comprising a leader module () and one or more follower modules (), the leader module () comprising a first oscillator () configured to provide a first clock signal at a first frequency to each follower module (), each of the leader and follower modules comprising a phase locked loop, PLL, clock signal generator (), the PLL clock signal generator () comprising a divide by n clock divider () arranged to output 2n phase shifted clock signals () at a third frequency and a multiplexer () connected to receive the 2n phase shifted clock signals from the divide by n clock divider () and output a third clock signal () selected by an input phase select signal ().

Radar system

The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit () comprising: a clock signal generator () configured to provide an output clock signal () having a duty cycle; a duty cycle detector () arranged to receive the output clock signal () and provide an output flag if the duty cycle of the clock signal () is outside a predetermined range; a controller () arranged to provide a duty cycle select signal () to the clock signal generator () to cause the clock signal () to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector ().

Duty cycle detector self-testing

Embodiments are directed to a buffer circuit that includes a first circuit and a second circuit. The first and second circuits include sets of transistors along pairs of related signal paths, each of the transistors being driven in response to two related input signals having different but related phases. The first circuit generates a first related output signal in response to one of the pairs of related signal paths and the second circuit generates a second output signal in response to another of the pairs of related signal paths. The first and second circuits provide a linear transfer function across one of the first and one of the second sets of transistors via one of the first pair and second pair of related signal paths.

Apparatuses and methods involving buffer circuits with linear transfer functions

A hardware device includes a frequency lock loop (FLL) that includes a phase loop filter, and a phase lock loop (PLL) such as an all digital PLL (ADPLL) that includes a frequency loop filter. A controller provides a first control signal to the FLL and a second control signal to the PLL when the device operates the same. The device can also include a digital controlled oscillator (DCO) and part of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a divider receive an input from the DCO. The controller forms a first loop with the first filter, the TDC, and the divider, and the controller forms a second loop with the second filter, the TDC, and the divider.

All digital phase locked loop (ADPLL) with frequency locked loop

A low-pass filter comprising: a filter input terminal; a filter output terminal; a filter FET configured to provide a resistance between the filter input terminal and the filter output terminal; a filter capacitor connected between the filter output terminal and a reference terminal; a bias FET configured to provide a bias voltage to the filter FET; a buffer connected between the filter input terminal and the bias FET, the buffer configured to source a bias current for the bias FET; and an offset voltage source configured to contribute to the bias voltage provided to the filter FET.

Low-pass filter

Level-shifting devices and methods allow signals to be passed between input/output (I/O) ports. One such device comprises a first output driver that drives a first I/O port in response to a first control signal. A second output driver drives a second I/O port in response to a second control signal. A first comparator circuit, responsive to a first reference voltage and a voltage at the first I/O port, generates the second control signal. A limiter circuit limits driving of the second I/O port, by the second driver, to a limiting voltage that responsive to a the second I/O port over a first range of signaling voltages, and constrained to a set value over a second range. A voltage reference generating circuit generates a second reference voltage. A second comparator circuit generates the first control signal in response to the second reference voltage and the second I/O port.

Bidirectional input/output circuit

Methods, devices and circuits are provided for protection from backdrive current. One such device is subject to back voltage from an output node of the device and includes circuitry that is configured to compare the supply voltage node and the output node. In response to the comparison, the circuitry generates an output signal. Level shifted versions of the output signal are used to provide an output voltage corresponding to the higher of a supply voltage node and an output node. Switches are used to place the device in different modes in response to the output signal.

Growing community of inventors

Rosengarten, Germany

Andreas Johannes Köllmann