Infineon Technologies Ag

Giesecke+devrient Currency Technology Gmbh

Qimonda Ag

Andreas Jakobs

Hermann Ruckerbauer

Maksim Kuzmenka

Georg Braun

Wolfgang Koniger

Michael Knickrehm

Torsten Hinz

Ralf Linck

Eckehard Plaettner

Benaissa Zaryouh

Christian Weis

Erwin Demmeler

Jean-Marc Dortu

Manfred Menke

Markus Sperl

Srdjan Djordjevic

Thomas Hildebrandt

Mario Mönch

Thomas Janik

Jurgen Von Kremling

Wolfgang Königer

Eckehard Plättner

Christian Voellmer

Carsten Nadolny

Helmut-Karl Reinisch

Simon Rudolf

A method is provided for controlling a system or a device for recognizing, checking, counting, accounting and sorting objects of value, which can be automatically adapted to changing delivery and demand conditions. A control controls the transport paths and processing steps within the device with the aid of conveyor plants and corresponding diverters and optimizes them in such a way that the objects of value are transported in a targeted fashion to the processing stages which are necessary for the processing of the objects of value. The control takes into account information about the components of the device as well as the inbound-delivered objects of value and the objects of value to be delivered outbound in order to ensure optimal processing of the objects of value or to deliver ordered packs of objects of value outbound as quickly as possible.

Controlling a system for handling valuable objects and preparing/outputting packs of valuable objects

The filling of value documents cassettes involves a cassette receiving device for receiving a value document cassette and a gripping device for transporting a value document stack from a value document container into the value document cassette. The apparatus optionally has a formatting device for the automatic alignment of a value document stack removed from the value document container before the stack is inserted in the value document cassette. A finger element is attached to the transport device of the gripping device, and besides the gripping device, the finger element is guided into the value document cassette before the value documents are inserted.

Filling of boxes for valuable documents

An assembly and a method for processing value documents such that the assembly has a transport apparatus for value-document receptacles which forms a cyclically circulating transport loop for the value-document receptacles. At least one checking apparatus for checking value documents is connected to the transport apparatus in such a manner that a respective value-document stack, possibly together with its value-document receptacle, can be transported via the respective transport interface from the cyclically circulating transport loop to the respective checking apparatus and/or from the respective checking apparatus to the cyclically circulating transport loop. The cyclically circulating transport loop is self-contained in such a manner that the value-document receptacles can circulate around the cyclically circulating transport loop several times in the same direction of circulation, and thus allows a temporally flexible removal of the respective value-document stack.

Assembly and method for processing value documents

An arrangement for processing of value documents at a preparation station, prior to their processing by means of a value document processing apparatus, involves inserting the value documents into a container divided into several storage regions. The value documents of the respective deposit are removed at the preparation station from delivery containers which respectively include a unique deposit identification. A monitoring device automatically captures into which storage region of the value document container the value documents are inserted. A protocol device connected to the monitoring device links the respective deposit identification to the container identification and to the respective storage region identification and transmits this linking information to a control device or to an accounting device, which assigns the value documents present in the respective storage region of the respective value document container to the respective deposit with the aid of the linking information transmitted by the protocol device.

Arrangement and method for processing security documents

An apparatus and method for filling containers with value documents and to a system for processing value documents, wherein the apparatus has: a container receiving device which is adapted to receive a container stack having two or several containers for receiving value documents, a lid receiving device which is adapted to receive a lid stack having two or several lids for closing the containers, a container removal device which is adapted to remove, preferably, the respectively lowermost container from the container stack, a closing device and a transport device which is adapted to convey the container removed from the container stack to a filling station, in which the container can be filled with value documents, and to convey the container filled with value documents to the closing device which is adapted to remove a lid from the lid stack and close the filled container with the removed lid.

Device and method for filling containers with value documents, in particular banknotes, and system for processing value documents

A method of controlling an analog signal in an integrated circuit includes generating a first control signal having a first predetermined duration within the integrated circuit. The first control signal is configured to cause the analog signal to have a first signal level. The first signal level is compared to a level of a target signal. A second control signal is generated within the integrated circuit based on a result of the comparison. The second control signal is configured to cause the analog signal to have a second signal level. The second control signal has a second predetermined duration that is different than the first predetermined duration.

Controlling an analog signal in an integrated circuit

An integrated circuit includes a chain of delay elements, a first phase detector, and a controller. The chain of delay elements is configured to delay an input clock signal for providing an output clock signal phase shifted with respect to the input clock signal by a selected value. The first phase detector is configured to provide a common control signal to each delay element based on a phase difference between the input clock signal and a signal output from one of the delay elements to adjust a delay of each delay element. The controller is configured to provide an independent control signal to each delay element to individually adjust the delay of each delay element such that the delay of each delay element is equal.

Delay locked loop

A buffer component for a memory module having a plurality of memory components includes item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the group of the plurality of memory components.

Buffer component for a memory module, and a memory module and a memory system having such buffer component

The invention describes a method for adjusting signal propagation times in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines for the purpose of transmitting control and data signals and at least one time reference signal. In line with the invention, the propagation time differences between connecting lines are ascertained from the result of echo measurements. To this end a respective transmitted pulse is applied to one end, selected as the transmission end, of the connecting lines in question, while the other end of the connecting lines in question is respectively terminated with a reflective termination. At the transmission end, the echo time which elapses between one edge of the transmitted pulse and the appearance of this edge's echo reflected from the other end is measured. On the basis of the ascertained propagation time differences, regulatable delay devices are set in order to compensate for these propagation time differences. The subject matter of the invention is also circuit arrangements for performing this method.

Method and circuit arrangements for adjusting signal propagation times in a memory system

One embodiment of the invention relates to a RAM memory circuit. A memory circuit includes a multiplicity of memory cells which can be selectively addressed, I/O circuitry for data; a clock input for receiving a system clock signal; a reception sampling circuit for sampling the received data using a reception strobe signal; and a reception strobe signal generating device which internally generates the reception strobe signal with synchronization with the received system clock signal.

Synchronous RAM memory circuit

A Phase shifter for generating a phase-shifted, in particular phase-delayed, output signal from an input signal is disclosed. In one embodiment, the phase shifter includes a first delay line and at least one further delay line with respectively cascaded delay elements that form a U-shaped signal path along which at least one delay element is adapted to be controlled to be optionally opening or closing. A phase discriminator located at the input side of which a clock signal and a signal from one of the delay lines can be applied, and the output side of which is connected with a respective control input of the delay elements. The clock signal can also be applied to the first delay line, so that a feedback loop is formed by the phase discriminator and at least one of the delay lines. The input signal can be applied to the delay line whose signal output is not connected with the phase discriminator, and the output signal can be output therefrom.

Phase shifter

A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.

Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted

The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group. The sum of the electrical signal propagation times for the actuating signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips, and control means for controlling the respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as the data signals via the bus inside the module when data are being written and read.

Semiconductor memory module

The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

DLL circuit for providing an adjustable phase relationship with respect to a periodic input signal

A memory module, which enables a module-internal, cross-chip electrical functional test of a plurality of integrated memory chips arranged on a printed circuit board of the memory module, includes a test device arranged separately from the memory chips on the printed circuit board. The test device relies on a clock signal provided by an external tester and generates the test signals required for carrying out the functional test and forwards the signals via control lines, address lines, data lines, and lines for the selection of individual memory chips to the latter. The partial integration of test functions into the test device enables a greater independence with respect to external electromagnetic interference influences without the space requirement of the memory module being increased overmuch.

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Munich, Germany

Andreas Jakobs