Koninklijke Philips Corporation N.v.

U.S. Philips Corporation

Nxp B.v.

Koninklijke Philips Electronics N.v.

Andreas Hubertus Montree

Pierre Hermanus Woerlee

Jurriaan Schmitz

Arjen Boogaard

Jan Johannes Van Den Broek

Willem Reindert De Wild

Johannes Nicolaas Huiberts

Martinus Hermanus Wilhelmus Maria Van Delden

Erwin Hijzen

Coen Theodorus Hubertus Fransiscus Liedenbaum

Raymond J E Hueting

Philippe Meunier-Beillard

Gerwin Hermanus Gelinck

Jan Willem Slotboom

Jan W Slotboom

Michel Marcel Jose Decre

Prabhat Agarwal

Jacobus Bernardus Giesbers

Martin Hillebrand Blees

Michael A A In'T Zandt

Paulus A Van Der Plas

Gerjan Franciscus Arthur Van De Walle

Casparus A H Juffermans

Godefridus A Hurkx

Gerrit E J Koops

Richard Antonius Fransiscus Van Der Rijt

Coen Theodorus Hubertus Franciscus Liedenbaum

Nicole A Wils

Gerjan F A Van De Walle

The invention relates to a semiconductor device () with a semiconductor body () comprising a bipolar transistor with an emitter region (), a base region () and a collector region () of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region () is positioned above or below the base region (), and the collector region () laterally borders the base region (). According to the invention, the base region () comprises a highly doped subregion (A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (A) extends laterally as far as the collector region (). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 10and about 10at/cm, and the thickness of the sub-region (A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device ().

Bipolar transistor and method of manufacturing the same

The electronic device comprises a thin-film transistor () and can be obtained from two substrates (). In order to preclude delamination at a non-adhesive interface between a metal pattern () and an organic layer (), the metal pattern () comprises apertures (). Through these apertures (), adhesion between the organic layer () and organic material at the surface () of one of the substrates () can be brought about. The electronic device can be manufactured by use of microcontact printing.

Thin film transistor device and method of making the same

A vertical insulated gate transistor is manufactured by providing a trench () extending through a source layer () and a channel layer () towards a drain layer (). A spacer etch is used to form gate portions () along the trench side walls, a dielectric material () is filled into the trench between the sidewalls gate portions (), and a gate electrical connection layer () is formed at the top of the trench electrically connecting the gate portions () across the trench.

Vertical insulated gate transistor and manufacturing method

A vertical interconnect () in an electronic device () is manufactured non-photolithographically. This is done by modifying a surface () of either a metal layer () or an intermediate layer of an electrically insulating material (), and subsequently depositing a composition with a first and a second polymer. Phase separation of the two polymers will lead to a first () and a second sub-layer (), of which the first sub-layer () is removed. An upper layer () of electrically conducting material can be deposited then or after a further etching step. This results in the vertical interconnect ().

Method of manufacturing an electronic device

The electronic device ( ) has a layer ( ) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer ( ) has a first electrically conducting areas ( ), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area ( ), comprising the material in the amorphous state. The layer ( ) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer ( ), electrically conductive areas of the layer can be strengthened by electroplating.

Electronic device, and method of patterning a first layer

In a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a transistor comprising a gate structure a patterned layer is applied defining the area of the gate structure Subsequently, a dielectric layer is applied in such a way, that the thickness of the dielectric layer next to the patterned layer is substantially equally large or larger than the height of the patterned layer which dielectric layer is removed over part of its thickness until the patterned layer is exposed. Then, the patterned layer is subjected to a material removing treatment, thereby forming a recess in the dielectric layer and a contact window is provided in the dielectric layer. A conductive layer is applied filling the recess and the contact window which conductive layer is subsequently shaped into the gate structure and a contact structure establishing an electrical contact with the surface of the semiconductor body

Method of manufacturing a semiconductor device

Passive component

In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD implantation. The halo implant, however, decreases the analog performance of transistors. To combine suppression of short-channel effects with a high analog performance, it is proposed to provide only transistors T , which are not intended for analog functions with the halo implant ( ), and to mask the analog transistors T with a mask ( ) against the halo implant. To avoid short-channel effects in T , this transistor is provided with a channel whose length is larger than that of transistor T .

Integrated circuit

In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region of a first conductivity type is defined at the surface of the semiconductor body , and a patterned layer is applied consisting of refractory material, which patterned layer defines the area of the planned gate to be provided at a later stage of the process and acts as a mask during the formation of a source zone and a drain zone of a second conductivity type in the semiconductor body In a next step, a dielectric layer is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer at the area of the planned gate. Then, impurities are introduced via the recess into the channel region of the semiconductor body in a self-registered way by using the dielectric layer , as a mask and an insulating layer is applied, forming the gate dielectric, on which insulating layer a conductive layer is applied thereby filling the recess, which conductive layer is shaped into the gate of the transistor.

In a method of manufacturing a semiconductor device comprising a non-volatile memory element, an active region of a first conductivity type is defined at a surface of a semiconductor body , and a patterned layer is applied, which patterned layer acts as a mask during the formation of a source zone and a drain zone of a second conductivity type in the semiconductor body . Then, a dielectric layer is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer . In this recess a first insulating layer is applied providing a floating gate dielectric , to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer , which first conductive layer is shaped into a floating gate by means of masked etching. The floating gate has a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and sidewall portions extending substantially perpendicularly to the surface of the semiconductor body . In a next step, the floating gate is covered with a second insulating layer providing an inter-gate dielectric , to which second insulating layer a second conductive layer is applied, which is shaped into an overlapping control gate . The control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone of the memory element.

Amorphous or polycrystalline silicon layers are sometimes used in the metallization steps of IC processes, for example as antireflex coatings or as etching stopper layers for etching back of tungsten. A problem is that such a layer cannot be provided by CVD or LPCVD on account of the high deposition temperature which is not compatible with standard Al metallizations. Other deposition techniques, such as sputtering or plasma CVD, often lead to a lesser material quality, a longer processing time per wafer, or a worse step covering. According to the invention, the layer is provided by CVD or LPCVD at a temperature below 500&deg; C. under the addition of Ge. The Ge,Si,layer (,) thus obtained is found to have good properties as regards step covering, optical aspects, electrical aspects, and etching aspects, and is compatible with any Al metallization (,) already present.

In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type. In a next step, a dielectric layer is applied, which is removed over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region and is exposed, after which the silicon-containing first active region are removed, thereby forming a recess in the dielectric layer. Subsequently, a second insulating layer is applied at the second active region providing an inter-gate dielectric of the memory element, and a third insulating layer is applied at the first active region providing a gate dielectric of the transistor. After formation of the gate dielectric and the inter-gate dielectric, a conductive layer is applied which is shaped into a gate of the transistor at the first active region and a control gate of the memory element at the second active region.

Method of manufacturing a nonvolatile memory

In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (,) and a nitride layer (,) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (,).

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Eindhoven, Netherlands

Andreas Hubertus Montree