Lsi Logic Corporation

Andreas Hils

Claus Pribbernow

Stefan G Auracher

Juergen Dirks

Manisha R Patel

James T Imper

Joerg Huth

A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying a second of the clockable circuit cells in the design representation. The second clockable circuit cell may have a clock timing dependent relation relative to the first clockable circuit cell. The method may further comprise configuring the clock signal supply network. The clock signal supply network may be configured to supply respective clock signals to the first and said second clockable circuit cells. The clock signal supply network may be configured to route the respective clock signals such that a timing difference between the respective clock signals is protected from process, voltage and temperature (PVT) influences.

Placement of a clock signal supply network during design of integrated circuits

The present invention may generally provide a processor circuit comprising a processor, a first bus, a bus pipeline stage, and a second bus. The first bus may be coupled to the processor. The bus pipeline stage may be coupled between the first bus and the second bus and configured to delay an access between the first bus and the second bus at least one pipeline cycle.

Bus interface for processor

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Integrated circuits, and design and manufacture thereof

The invention relates to an integrated circuit including a hard-core and a peripheral circuit. The hard-core and the peripheral circuit each include respective registers, which are couplable for scan chain testing by respective scan chain paths within the core and within the peripheral circuit. In order to avoid timing problems between the two scan chain paths, a lock-up latch is provided within the hard-core. The lock-up latch has an input coupled to the last register in the scan chain path within the hard-core, and an output coupled to the first register in the scan chain path in the peripheral circuit. The lock-up latch forms part of the hard-core and is clocked by the same clock signal as the last register in the hard-core scan chain path.

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Unterhaching, Germany

Andreas Hils