Mentor Graphics Corporation

Koninklijke Philips Corporation N.V.

Nxp B.v.

Siemens Industry Software Gmbh

Andreas Glowatz

Friedrich Hapke

Wu-Tung Cheng

Xijiang Lin

Hendrikus Petrus Elisabeth Vranken

Rene Krenz-Baath

Takeo Kobayashi

Juergen Schloeffel

Ruediger Solbach

Wilfried Redemund

This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

Library cell modeling for transistor-level test pattern generation

Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.

Cell-aware fault model generation for delay faults

Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.

Multi-targeting boolean satisfiability-based test pattern generation

An apparatus for testing an integrated circuit is disclosed. The apparatus includes a compactor to compress test responses from a circuit under test that is part of an integrated circuit.

Method and system for selectively masking test responses

In an arrangement for testing an integrated circuit comprising at least two circuit sections ( ) which in normal operation operate with at least two different clock signals, a minimal number of test runs for testing the integrated circuit is required because the integrated circuit to be tested is formed in such a way that each clock signal can be individually switched on and off during a test by test software provided in the arrangement, a software model of the circuit to be tested is provided in the arrangement, which software model comprises an X generator ( ) for those circuit components ( ) whose mode of operation is influenced by a plurality of clock signals and their skew behavior, which X generator is activated and supplies an X signal when more than one clock signal influencing the mode of operation of the circuit components ( ) during testing is activated, while, during testing, the test software initially activates all clock signals and evaluates test results for those circuit components ( ) for which no X signal appears in the software model ( ), and because for those circuit components ( ) for which an X signal appeared in the software model ( ) during testing with all clock signals, the test software performs a plurality of test runs in which each time only one or more of the clock signals influencing the mode of operation of the circuit component ( ) is/are activated and evaluates only those tests of the circuit components ( ) of the circuit for which no X signal appears in the software model ( ).

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Heidenau, Germany

Andreas Glowatz