Microsoft Technology Licensing, LLC

Hewlett-packard Development Company, L.p.

Vmware, Inc.

Google Inc.

Elwha LLC

The Brain Window, Inc.

University of Pittsburgh

Photonanoscopy Corporation

Andreas Georg Nowatzyk

Kourosh Gharachorloo

Luiz Andre Barroso

Pratap Subrahmanyam

Isam Wadih Akkawi

Rod G Fleck

Steven Nabil Bathiche

Anoop Gupta

Paul Henry Dietz

Olivier Temam

Lowell L Wood, Jr

Roderick A Hyde

Clarence T Tegreene

Jordin T Kare

Nathan P Myhrvold

Muriel Y Ishikawa

Victoria Y H Wood

Charles Whitmer

Kenneth Paul Hinckley

David Douglas Bohn

Robert C Petroski

Jesse R Cheatham, Iii

Philip Andrew Eckhoff

Craig J Mundie

Matthew Graham Dyor

Hrvoje Benko

Bruce M Schena

Lawrence K Lam

William Riis Hamburgen

Rajesh Venkatasubramanian

Irina Calciu

Robert J Stets, Jr

Mosur Kumaraswamy Ravishankar

Venkata Subhash Reddy Peddamallu

Charles Patrick Thacker

Danny Allen Reed

Adarsh Seethanadi Nayak

Nishchay Dua

Ravi Narayanaswami

Ramakrishna Rao Kotla

Uday Kumar Dasari

Fang Yu

Jeffrey Y Hayashida

John Stuart Fitch

John C Tang

Gina Danielle Venolia

Michael Wei

Kelvin Kwong

Sasa Junuzovic

Thomas Lee Rodeheffer

Yi Tao

Daniel R Delling

Gavin Jancke

Andrew V Goldberg

James Cooper

Renato F Werneck

Kori Inkpen Quinn

George DeWitt Stetten

Aaron C Hoff

Joel Stephen Pritchett

Amy Tai

Kiarash Vakhshouri

Avi Hecht

Ali Najafi

Jonathan Nivet

Luiz Andr&eacute; Barroso

Yijiang Yuan

Sreekanth Setty

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.

Yield improvements for three-dimensionally stacked neural network accelerators

While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

Coherence-based attack detection

Described herein are systems, methods, and software to manage time calibration associated with an oscillator of a computing system. In one example, a computing system monitors clock cycles for an oscillator on the computing system, receives timing messages from a server, and calculates the frequency of the oscillator at intervals based on the monitored clock cycles and timing messages. The computing system further identifies a temperature from a temperature sensor at each of the intervals and generates a function to demonstrate frequency of the oscillator versus temperatures from the temperature sensor based on the identified temperatures and frequencies at the intervals.

Clock calibration in a computing system using temperature sensors

A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

Smart prefetching for remote memory

A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.

Coherence-based dynamic code rewriting, tracing and code coverage

A three dimensional neural network accelerator that includes a first neural network accelerator tile that includes a first transmission coil, and a second neural network accelerator tile that includes a second transmission coil, wherein the first neural network accelerator tile is adjacent to and aligned vertically with the second neural network accelerator tile, and wherein the first transmission coil is configured to wirelessly communicate with the second transmission coil via inductive coupling.

Neural network accelerator tile architecture with three-dimensional stacking

The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.

Method and system for tracking state of cache lines

In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.

Techinques for tracking frequently accessed memory

In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

Low latency host processor to coherent device interaction

Techniques for implementing hardware-assisted memory disaggregation with recovery from network failures/problems are provided. In one set of embodiments, a hardware controller of a computer system can maintain a copy of a 'remote memory' of the computer system (i.e., a section of the physical memory address space of the computer system that maps to a portion of the physical system memory of a remote computer system) in a local backup memory. The backup memory may be implemented using a non-volatile memory that is slower, but also less expensive, than conventional dynamic random-access memory (DRAM). Then, if the hardware controller is unable to retrieve data in the remote memory from the remote computer system within a specified time window due to, e.g., a network failure or other problem, the hardware controller can retrieve the data from the backup memory, thereby avoiding a hardware error condition (and potential application/system crash).

Hardware-assisted memory disaggregation with recovery from network failures using non-volatile memory

Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.

A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.

Coherence-based cache-line Copy-on-Write

A near-eye display system includes a see-through display, an image source, a background light sensor, a selective background occluder including a first liquid crystal panel and a second liquid crystal panel positioned between a pair of polarizers, and a computing device including instructions executable by a logic subsystem to determine a shape and a position of an occlusion area based upon a virtual object to be displayed, obtain a first and a second birefringence pattern for the first and the second liquid crystal panels, produce the occlusion area by applying the birefringence patterns to the liquid crystal panels, and display the virtual object in a location visually overlapping with the occlusion area.

Selective occlusion system for augmented reality devices

Growing community of inventors

San Jose, CA, United States of America

Andreas Georg Nowatzyk