Elmos Semiconductor Ag

Andreas Gehrmann

Erhard Muesch

Erhard Müsch

Ralf Bornefeld

The MOS transistor with high voltage sustaining capability and low closing resistance comprises a substrate doped with charge carriers of a first line type. In the substrate drain and source regions are configured doped with charge carriers of a second line type opposed to the first line type. Further, the MOS transistor is provided with a gate electrode arranged in the region between the drain and the source regions on the substrate and comprising a drain-side end region. A drain extension region is doped with charge carriers of the second line type, connected with the drain region and extends to below the drain-side end of the gate electrode. The drain extension region is produced by an ion implantation process comprising at least a first implantation step. The drain extension region comprises in its region near the top side and facing the top side of the substrate a lower doping material concentration than in its region below the region near the top side.

MOS transistor with high voltage sustaining capability and low on-state resistance

In a channel well of a semiconductive substrate, source, drain and gate electrodes are formed. Below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship, said partial regions bordering on the gate electrode region and extending through the channel well region into the region of the substrate bordering on the channel well region from below.

Junction field effect transistor or JFET with a well which has graded doping directly beneath the gate electrode

The NMOS transistor is provided with a semiconducting substrate (12) which is p-doped and comprises a top side (14), and with a first region (16) which is n-doped and placed into the substrate by diffusion from the top side (14) of the substrate (12). Further, the transistor comprises a second region (18) arranged within the n-conducting region (16), which is n-doped and introduced into the substrate from the top side (14) of the substrate (12), and a field oxide layer (20) which is arranged on the top side (14) of the substrate (12) and limits the p-conducting region (16) on all sides. The top side comprises a source region (22) and a drain region (24) which are n-doped and arranged within the p-conducting region (18) at a distance to each other. A gate oxide layer (26) is arranged on the top side (14) of the substrate (12) between the source and the drain regions (22, 24). According to the invention it is envisaged that the p-conducting region (18) is placed into the n-conducting region (16) by means of ion implantation and that within the p-conducting region (18) the ion concentration on the top side (14) of the substrate (12) is smaller than that at the lower limit, located within the substrate (12), between the n-conducting region (16) and the p-conducting region (18).

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Dortmund, Germany

Andreas Gehrmann