Sun Microsystems, Inc.

Compaq Computer Corporation, Inc.

Andreas G Nowatzyk

Fong Pong

Ashley N Saulsbury

Michael W Parkin

In a system for communicating optically encoded data among a network of nodes, the nodes are connected to each other by optical transmit and receive fibers. Each node includes a laser, a transmitter, and a receiver connected to the transmitters of the other nodes by a fiber stretcher. The rate at which the laser generates light pulses is controlled by a frequency control signal supplied to an oscillator connected to the laser. The delay from the transmitters to the receivers is controlled by a phase control signal supplied to the fiber stretcher connected to the receive fiber. The transmitter connected to the transmit fiber selective delays the pulses into a plurality of time multiplexed channels. The receiver connected to the fiber stretcher selectively detects the pulses in the time multiplexed channels while all of the pulses of all of the nodes are globally synchronized in all of the time multiplexed channels in frequency and phase using the frequency and phase control signals.

System for optical time domain multiplexing of digital signals

An integrated processor/memory device comprising a main memory, a CPU, and a full width cache. The main memory comprises main memory banks. Each of the main memory banks stores rows of words. The rows are a predetermined number of words wide. The cache comprises cache banks. Each of the cache banks stores one or more cache lines of words. Each of the cache lines has a corresponding row in the corresponding main memory bank. The cache lines are the predetermined number of words wide. When the CPU issues an address in the address space of the corresponding main memory bank, the cache bank determines from the address and the tags of the cache lines whether a cache bank hit or a cache miss has occurred in the cache bank. When a cache bank miss occurs, the cache bank replaces a victim cache line of the cache lines with a new cache line that comprises the corresponding row of the corresponding memory bank specified by the issued address.

Processor/memory device with integrated CPU, main memory, and full width cache and associated method

An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. When the CPU issues an address in the address space of the main memory, the victim cache determines whether a victim cache hit or miss has occurred in the victim cache. And, when a victim cache miss occurs, the victim cache replaces a selected victim cache sub-line of the victim cache sub-lines in the victim cache with a new victim cache sub-line. The primary cache comprises primary cache banks. Each of the primary cache banks stores one or more cache lines of words. Each cache line has a corresponding memory location in the corresponding main memory bank. When the CPU issues an address in the portion of the address space of the corresponding main memory bank, the corresponding primary cache bank determines whether a cache hit or a cache miss has occurred. When a cache miss occurs, the primary cache bank replaces a victim cache line of the cache lines in the primary cache bank with a new cache line from the corresponding memory location in the corresponding main memory bank specified by the issued address and routs a sub-line of the victim cache line as the new victim cache sub-line.

Integrated processor/memory device with victim data cache

An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for communicating with adjacent nodes in a network. Linked ports between two nodes provide a continuous stream of information with idle packets filling non-data transfer cases. The logic of the interconnect controller provides for adaptive routing and to topology independence and allows for the sharing of a common clock for synchronizing the packet transmission.

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Mountain View, CA, United States of America

Andreas G Nowatzyk