Arm Limited

Atmel Corporation

Andreas Due Engh-Halstvedt

Jorn Nystad

Olof Henrik Uhrenholt

Frank Klaeboe Langtind

Frode Heggelund

Edvard Fielding

Alexander Eugene Chalfin

Sandeep Kakarlapudi

Jørn Nystad

Edvard Sorgard

Lars Oskar Flordal

Aske Simon Christensen

Mark Underwood

Thomas Jeremy Olson

Nebojsa Makljenovic

Simon Alex Charles

Simon James Jones

Ian Rudolf Bratt

Sean Tristram Ellis

Jakob Axel Fries

Peter William Harris

Erik Knutsen Renno

Oskar Lars Flordal

Christian Vik Grovdal

Andreas Loeve Selvik

David James Bermingham

Marius Bjorge

Daren Croxford

David Raymond Lutz

Christopher Neal Hinds

Neil Burgess

Frode Milch Pedersen

Toni Viki Brkic

Rune Holm

Ian Victor Devereux

William Robert Stoye

Andrew Burdass

Samuel Martin

Oyvind Strom

Hakan Persson

Isidoros Sideris

Ronny Pedersen

Antonio Garcia Guirado

Quinn Carter

Robert Elliott

Tord Kvestad Øygard

Michel Patrick Gabriel Emil Iwaniec

Amir Kleen

Alexander Galazin

Andreas Danner Nilsen

Kenneth Edvard Østby

Are Arseth

Antonio García Guirado

Vatsalya Prasad

Lukasz Kulasza

Shan Wu

Shareef Justin Jalloq

Jörg Wagner

Arne Bergene Fossaa

Arne Aas

Michael Stokes

Henrik Ohlsson

Edvard Feilding

Havard Skinnemoen

Daniel Fedai Larsen

Philip Michael Watts

A data processor, such as a graphics processor, is disclosed. The data processor includes a set of one or more counters, and a control circuit that maintains a cache-like pool of corresponding entries. In response to a request for a counter, the control circuit may allocate an entry of the cache-like pool to thereby allocate a counter of the set.

Providing counters in a data processor

A data processing system is disclosed that includes one or more processors that can perform producer processes to produce work and consumer processes that can consume work produced by a producer process. The system includes a pool of plural communication resources that may be used for communications between a producer process and a consumer process. The system tracks the usage of communication resources of the pool of communication resources, and allocates a communication resource from the pool of communication resources based on the tracking.

Data processing systems

A data processor comprising an execution enginefor executing programs for execution threads and one or more cachesoperable to store data values for use when executing program instructions to perform processing operations for execution threads. The data processor further comprises a thread throttling control unitconfigured to monitor the operation of the cachesduring execution of programs for execution threads, and to control the issuing of instructions for execution threads to the execution engine for executing a program based on the monitoring of the operation of the caches during execution of the program.

Data processors

A data processing system includes an external memory system, a processor and an internal memory system. The internal memory system includes an internal memory that stores data for use by the processor when performing data processing operations. The internal memory system also includes a data encoder associated with the internal memory. The data encoder reads data from the external memory system to the data encoder and returns the data to the external memory system from the data encoder, without storing the data in the internal memory.

Data processing systems including a data encoder that reads in data from and returns data to an external memory system

A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, 'tile elimination' data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.

Graphics processors

A data processing system includes a cache system configured to transfer data stored in the memory system to a processor and to transfer data from the processor to the memory system. The cache system comprises a cache and a data encoder associated with the cache that is configured to encode uncompressed data from the cache for storing in the memory system in a compressed format, and decode compressed data from the memory system for storing in the cache in an uncompressed format.

Cache arrangement for data processing systems

When generating a graphics processing output, a sequence of one or more of primitives to be processed when generating the output is assembled from a set of vertex indices provided for the output based on primitive configuration information provided for the output, each assembled primitive of the sequence of assembled primitives comprising an identifier for the primitive and a set of one or more vertex indices for the primitive. One or more attributes for vertices of the assembled primitives are then shaded and fetched based on the vertex indices of the assembled primitives. The assembled primitives including their shaded fetched vertex attribute(s) are then provided to later stages of the graphics processing pipeline for processing.

Primitive assembly and vertex shading of vertex attributes in graphics processing systems

A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be 'recycled' for use by the pipeline.

Graphics processing

In a data processing system comprising a cache system configured to transfer data stored in a memory system to a processor and vice-versa, a processing unit operable to read data from a cache of the cache system can send a read request for data to the cache. The cache system, in response to the read request, determines whether the requested data is present in the cache. When the requested data is present in the cache, the cache system returns the data from the cache to the processing unit and invalidates the entry for the data in the cache. When the requested data is not present in the cache, the cache system returns an indication of that to the processing unit, without the cache system sending a request for the data towards the memory system.

Cache miss handling for read operations in data processing systems

When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Primitive data for rendering the primitive is then stored either in a combined data structure in memory that is associated with a plurality of different regions of the render output, or is stored in a respective data structure for each region of the render output it is determined the primitive should be rendered for. Which manner the primitive data is stored is determined in dependence on a property, e.g. a coverage, of the primitive.

Graphics processing systems

When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. For each region of the render output it is determined a primitive should be rendered for, geometry data for the primitive is stored in memory in a respective data structure for the region in a compressed form, such that the geometry data for the primitive to be rendered is stored in a compressed form, in a respective, different data structure for each different region of the render output it is determined the primitive should be rendered for.

When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Associated state data for rendering the primitive is stored in a 'state data' data structure in memory. For each region of the render output it is determined the primitive should be rendered for, a reference to the associated state data for rendering the primitive is stored in a respective, different data structure for each different region of the render output it is determined the primitive should be rendered for.

A data processing system includes a memory and a processor in communication with the memory. The processor is configured to, when storing an array of data in the memory, produce information representative of the content of a block of data representing a particular region of the array of data, write the block of data to a data structure in the memory, and write the information representative of the content of the block of data to the data structure.

A method of operating a graphics processor that is configured to execute a graphics processing pipeline is provided. The method comprises the graphics processor reading, from an index buffer in external memory, a block of data comprising plural sets of indices, each set of indices comprising a sequence of indices indexing a set of vertices that defines a primitive of a plurality of primitives to be processed by the graphics processing pipeline. The graphics processor compresses the block of data to form a compressed version of the block of data, and stores the compressed version of the block of data in an internal memory of the graphics processor.

Index buffers in graphics processing systems

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Trondheim, Norway

Andreas Due Engh-Halstvedt