International Business Machines Corporation

Globalfoundries U.S. Inc.

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Andreas Daniel Stricker

Alain F Loiseau

Marwan H Khater

Ephrem G Gebreselasie

Gregory Gower Freeman

Yusheng Bian

Qizhi Liu

Jae-Sung Rieh

Robert J Gauthier, Jr

Renata A Camillo-Castillo

Kathryn Turner Schonenberg

Alvin Jose Joseph

James Stuart Dunn

Richard A Phelps

Francois Pagette

Joseph M Lukaitis

Icko E T Iben

David Louis Harame

Randy William Mann

Stephen Arthur St Onge

Nicholas A Polomoff

Robert J Purtell

Peter John Geiss

Bo Peng

Richard A Poro, Iii

Steven H Voldman

Hanyi Ding

Benjamin V Fasano

Rajendran Krishnasamy

Yun Shi

Huajie Chen

Natalie Barbara Feilchenfeld

Karen A Nummy

Kenneth John Giewont

BethAnn Rainey

Mattias E Dahlstrom

Steven W Mittl

Erik Mattias Dahlstrom

Jae Kyu Cho

Mohamed Rabie

Ahmed Y Ginawi

Ajey Poovannummoottil Jacob

Judson Robert Holt

Robert Mark Rassel

Kiran V Chatty

Mujahid Muhammad

David Charles Sheridan

Michal Rakowski

Peter B Gray

Bradley Alan Orner

Kimball M Watson

Jessie Carrigan Rosenberg

Russell T Herrin

Won Suk Lee

Zhuojie Wu

Abdelsalam A Aboketaf

Beth Ann Rainey

Abu Thomas

Asif J Chowdhury

Shuren Hu

Anupam I Arora

Colleen Meagher

David B Riggs

Richard Antoine Poro

Min Woo

Stephen A STONGE

Jae-Sung c/o Ibm United Kingdom Ltd Rieh

The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. A passive optical guard is composed of a light absorbing material and is in proximity to the photonic component. The passive optical guard includes at least a portion in an active semiconductor layer of the semiconductor substrate and may be entirely below a first metal layer. The passive optical guard may include at least one of: a germanium body positioned at least partially in a silicon element in the active semiconductor layer, a silicon body having a high dopant concentration in the active semiconductor layer, and a polysilicon body having a high dopant concentration over the silicon body.

Photonic integrated circuit including passive optical guard

Structures for a photodetector or light absorber and methods of forming a structure for a photodetector or light absorber. The structure includes a pad, a waveguide core adjoined to the pad, and a light-absorbing layer on the pad. The waveguide core includes a first longitudinal axis, and the light-absorbing layer includes a second longitudinal axis and an end surface intersected by the second longitudinal axis. The end surface of the light-absorbing layer is positioned adjacent to the waveguide core. The first longitudinal axis of the first waveguide core is inclined relative to the second longitudinal axis of the light-absorbing layer and/or the end surface slanted relative to the second longitudinal axis.

Photodetectors and absorbers with slanted light incidence

A structure includes a polarization device such as a polarization splitter, a polarization combiner or a polarization splitter rotator including a waveguide having a light absorber at an end section with an at least hook shape, e.g., it can be hooked or spiral shape. The structure also includes another waveguide adjacent the stated waveguide. The hook or spiral shape acts as a light absorber that reduces undesired optical noise such as excessive light insertion loss and/or light scattering. The hook or spiral shape may also be used on supplemental waveguides used to further filter and/or refine an optical signal in one of the waveguides of the polarization device, e.g., downstream of an output section of the polarization splitter and/or rotator.

Structure with polarization device with light absorber with at least a hook shape

Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

Corner structures for an optical fiber groove and manufacturing methods thereof

Embodiments of the disclosure provide an integrated circuit (IC) structure, including an absorber layer separated from an optical grating coupler by a cladding material. The absorber is positioned to receive light reoriented through the optical grating coupler.

Integrated circuit structure with optical absorber layer over optical grating coupler

Embodiments of the disclosure provide an integrated circuit (IC) structure, including an optical medium for light signals; and an optical grating coupler coupled to the optical medium. The optical grating coupler is configured to reorient light from the optical medium. A cladding material is over the optical grating coupler. An absorber layer is over the cladding material, and vertically above the optical grating coupler.

Structures for a photodetector and methods of fabricating a structure for a photodetector. A photodetector may have a light-absorbing layer comprised of germanium. A waveguide core may be coupled to the light-absorbing layer. The waveguide core may be comprised of a dielectric material, such as silicon nitride. Another waveguide core, which may be comprised of a different material such as single-crystal silicon, may be coupled to the light-absorbing layer.

Multiple waveguide coupling to one or more photodetectors

Corner structures for an optical fiber groove

Embodiments of the disclosure provide a demultiplexer for processing a multiplexed optical input. The demultiplexer may include a plurality of Mach-Zehnder Interferometric (MZI) stages for converting the multiplexed optical input into a plurality of component optical signals. Each of the plurality of component optical signals corresponds to a respective wavelength-space component of the multiplexed optical input. A plurality of bandpass filters, each having a respective wavelength passband, may receive one of the plurality of component optical signals. The plurality of bandpass filters generates a plurality of demultiplexed optical signals based on the plurality of component optical signals.

Demultiplexer and related method to process multiplexed optical inputs

The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.

Electrostatic discharge clamp with reduced off-state power consumption

Embodiments of the disclosure provide a photonic integrated circuit (PIC) die including: a semiconductor substrate; active circuitry on the semiconductor substrate; an inter-level dielectric (ILD) over the semiconductor substrate and the active circuitry; a photonic element extending from the active circuitry on the semiconductor substrate; and a guard ring on the semiconductor substrate and within the ILD, the guard ring surrounding the active circuitry, the guard ring including: a conductive body, and a conductive bridge element extending over the photonic element.

Guard ring for photonic integrated circuit die

Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.

Space efficient and power spike resistant ESD power clamp with digitally timed latch

Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A tapered feature composed of a dielectric material is arranged over the waveguide. The tapered feature includes a sidewall that is angled relative to a longitudinal axis of the waveguide.

Waveguides including a patterned dielectric layer

Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Voltage balanced stacked clamp

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Essex Junction, VT, United States of America

Andreas Daniel Stricker