Xilinx, Inc.

Andreas Benno Kollegger

Ian D Miller

Jonathan C Harris

Stephen G Edwards

James E Jensen

Christopher R S Schanck

Donald J Davis

Conor C Wu

Yung-Sheng Yu

Christopher Robert Sunderland Schanck

A method of designing an integrated circuit using a general purpose programming language can include identifying a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined and access to the modeled global memory can be scheduled. The programmatic design can be translated into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.

Method of transforming software language constructs to functional hardware equivalents

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model () and identifying data input to each component specified in the language independent model to determine a latency for each component (). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself ().

Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations

A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language () and identifying a loop construct within the language independent model (). A determination can be made as to whether the loop construct is bounded (). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique ().

Determining hardware generated by high level language compilation through loop optimizations

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (, and). The language independent model can be scheduled such that each component is activated when both control and valid data arrive at the component (). An interface structure specifying a hardware interface through which devices external to the language independent model interact with a physical implementation of the language independent model can be defined and included in the language independent model ().

Generating hardware interfaces for designs specified in a high level language

A method of designing an integrated circuit using a general purpose programming language can include identifying () a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling () the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined () and access to the modeled global memory can be scheduled (). The programmatic design can be translated () into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.

The compilation of a high-level software-based description of an algorithm into efficient digital hardware implementation(s) is addressed. This is done through the definition of new semantics for software constructs with respect to hardware implementations. This approach allows a designer to work at a high level of abstraction, while the semantic model can be used to infer the resulting hardware implementation. These semantics are interpreted through the use of a compilation tool that analyzes the software description to generate a control and data flow graph. This graph is then the intermediate format used for optimizations, transformations and annotations. The resulting graph is then translated to either a register transfer level or a netlist-level description of the hardware implementation.

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Baltimore, MD, United States of America

Andreas Benno Kollegger