Infineon Technologies Ag

Andreas Baenisch

Semen Syroiezhin

Andreas Wickmann

Sabine Kling

Stephan Leuschner

Winfried Bakalski

Michael Bernhard Sommer

Florian Schamberger

Nikolay Ilkov

Peter Pfann

Hans-Dieter Wohlmuth

Uwe Mueller

Werner Obermaier

A regulated charge pump includes a comparator having a first input coupled to an output of the regulated charge pump, a second input configured for receiving a reference voltage, and an output for generating an output voltage representing a difference between a charging current of the regulated charge pump and a load current of a load coupled to the output of the regulated charge pump; a first converter having an input coupled to the output of the comparator, and an output connected to a control bus configured to indicate an adjustment of the charging current in response to the comparator output; and a driving stage having a first input coupled to the control bus, and an output for providing the charging current, wherein the output of the driving stage comprises the output of the regulated charge pump.

Regulated charge pump with adaptive drive strength

A method includes detecting a voltage at a configuration terminal of a mobile industry processor interface (MIPI) radio frequency front end (RFFE) device with a timing based on a MIPI RFFE signal received by the MIPI RFFE device, and setting an address for the MIPI RFFE device based on the detected voltage.

Method for MIPI RFFE address assignment and MIPI RFFE device

A circuit includes a switch coupled between a configuration terminal and an internal node. In a method of operation, the configuration terminal of the circuit is coupled to an internal node during a configuration phase and decoupled from the internal node during normal operation.

Circuit including configuration terminal and method

In accordance with an embodiment, a circuit includes: a replica input transistor, a first replica cascode transistor, an active current source, and an active cascode biasing circuit. The active current source is configured to set a current flowing through the first replica cascode transistor and the replica input transistor to a predetermined value by adjusting a voltage of a control node of the replica input transistor; and an active cascode biasing circuit including a first output coupled to the control node of the first replica cascode transistor, and the active cascode biasing circuit configured to set a drain voltage of the replica input transistor to a predetermined voltage by adjusting a voltage of the control node of the first replica cascode transistor.

System and method for biasing an RF circuit

A means of attachment for electrically contacting electronic components is disclosed. The means of attachment includes a carrier element and a number of elongated connecting elements. Each of the connecting elements is arranged on the carrier element and has an elongated body, which protrudes from the carrier element. Each of the connecting elements and the carrier element includes an electrically conductive surface.

Means of mounting for electronic components, arrangement and procedure

In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout being generated from layout changes of the first layout. The first group of error data is compared to the second group of error data and only error data that are different in the first and second groups is output for evaluation.

Method for reducing the evaluation outlay in the monitoring of layout changes for semiconductor chips

A data memory for storing data, having a memory cell array ( ), which comprises a large number of memory cells ( ), each of which can be addressed by means of a memory cell select transistor ( ) connected to a word line ( ) and to a bit line ( ) and which have a storage capacity for storing one data bit, the memory cell array ( ) containing redundant memory cells ( ), which are provided in order to replace memory cells ( ) which have been produced wrongly, by means of readdressing, and having read amplifiers ( ), which are in each case provided for the signal amplification of a data bit read from an addressed memory cell ( ) via an associated bit line ( ) and are supplied with a buffered supply voltage, the redundant memory cells ( ) which have not been readdressed being connected to the associated bit lines ( ) and additionally buffering the supply voltage for the read amplifiers ( ).

Data memory with redundant memory cells used for buffering a supply voltage

The present invention provides an integrated circuit with a plurality of active strip-shaped regions (S D S D S ) arranged in parallel next to one another; a contact level (K ) with a respective plurality of contacts ( ) arranged regularly in the longitudinal direction of the individual strip-shaped regions (S D S D S ); the contacts ( ) being arranged in the widthwise direction of the individual strip-shaped regions (S D S D S ) in such a way that the widthwise extent of corresponding contacts ( ) of neighboring regions varies.

Growing community of inventors

Munich, Germany

Andreas Baenisch