Intel Corporation

Other

Apple Inc.

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Intel IP Corporation

Google Inc.

Andreas Augustin

Reinhard Mahnkopf

Andreas Wolter

Bernd Waidhas

Thorsten Meyer

Georg Seidemann

Christian Geissler

Gerald Ofner

Thomas Wagner

Sonja Koller

Saravana Maruthamuthu

Christian Mueller

Josef Hagn

Stephan Stoeckl

Kilian Roth

Thomas Ort

Laurent Millou

Shilpa Talwar

Hosein Nikopour

Hans-Joachim Barth

Christian Drewes

Sven Albers

Kenneth Jay Stein

Michael D Armacost

Peter Baumgartner

Oner Orhan

Stefan Mueller-Weinfurtner

Gerald R Friese

John E Heidenreich, Iii

Peter Noest

Junyoung Nam

Gary Robert Hueckel

Veronica Sciriha

Reinhard Golly

Thomas Hauser

Michael Weber

Joachim Wehinger

Christian Müller

An electronic device may be provided with an antenna, a receiver, and baseband circuitry coupled to the receiver over a digital interface. The receiver may receive radio-frequency signals using the antenna and may generate digital in-phase and quadrature-phase (I/Q) samples from the radio-frequency signals. The I/Q samples may have a bit width and may be transmitted to the baseband circuitry over the digital interface. The baseband circuitry may evaluate a radio condition of the receiver based on the I/Q samples. The baseband circuitry may adjust the bit width of the I/Q samples based on the radio condition. For example, the baseband circuitry may decrease the bit width when wireless performance metric data falls below a threshold and/or may increase the bit width when the wireless performance metric data exceeds a threshold. This may minimize power consumed by the digital interface without sacrificing wireless performance.

Electronic devices with adjustable received sample bit width

Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.

Antenna with graded dielectirc and method of making the same

Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

Single metal cavity antenna in package connected to an integrated transceiver front-end

A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

Semiconductor packages, and methods for forming semiconductor packages

Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

Package integrated cavity resonator antenna

A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.

Resonant LC tank package and method of manufacture

A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.

Magnetic coils in locally thinned silicon bridges and methods of assembling same

A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

Patch antennas stitched to systems in packages and methods of assembling same

The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.

Semiconductor inductors

A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

Component magnetic shielding for microelectronic devices

This disclosure relates to a data processing device, comprising: a digital front end (DFE) configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols; a baseband (BB) circuitry configured to process the digital data in baseband; and a digital interface between the DFE and the BB circuitry, wherein the DFE comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry.

Techniques for data compression

Growing community of inventors

Munich, Germany

Andreas Augustin