Micron Technology Incorporated

Andrea Vigilante

Gianluca Scalisi

Mauro Luigi Sali

Andrea Pozzato

Andrea Salvioni

Luca Porzio

Roberto Izzi

Marco Onorato

Sean L Manion

Massimo Zucchinali

Bryan D Butler

Alfredo Palazzo

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Latency reduction of boot procedures for memory systems

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Memory system tester using test pad real time monitoring

A testing device comprises test interface circuitry, probe circuitry, and initiate state machine circuitry. The test interface circuitry is configured to receive NAND signaling when operatively coupled to a M-NAND memory device under test and to operate the M-NAND memory device under test to receive memory access requests and to provide status or data at the same rate it receives memory access requests. The probe circuitry is configured to detect memory operations of the memory device under test. The finite state machine circuitry is operatively coupled to the probe circuitry and is configured to advance through multiple circuit states according to the detected memory operations; and log memory events of the memory device under test according to the circuit states.

Managed-NAND real time analyzer and method

A variety of applications can include a system having a system platform to which a memory system can be attached for operation of the system. With the memory system removed from the system platform or before being attached to the system platform, an interposer can be connected at the location for the memory system on the system platform to facilitate testing of the system with respect to the memory system. The interposer can include a set of electrical connectors embedded on a first side of the interposer to connect to the system platform and a connector embedded on a second side of the interposer opposite the first side, where the connector allows coupling to an external platform to convey signals between the system platform and the external platform. Additional apparatus, systems, and methods are disclosed.

Interconnect system

Growing community of inventors

Milan, Italy

Andrea Vigilante