Microchip Technology Inc.

University of California

Andrea Panigada

Daniel R Meacham

Jorge Grilo

Ian Galton

Bogdan Bolocan

David Shih

Jason Remple

Daniel Meacham

A slave device includes an SPI bus with a mode detection circuit configured to detect an SPI operating mode that has been applied by a master device. The slave device is configurable to operate in a first or a second mode depending on the detection of the SPI operating mode as applied by the master device.

Method and system for enhanced SPI communication

An analog input stage has m differential input channels, wherein m&#x3e;1. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.

Sampling input stage with multiple channels

A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

Modified dynamic element matching for reduced latency in a pipeline analog to digital converter

An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.

Distributed bootstrap switch

A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order.

Multichannel analog to digital converter apparatus and method for using

A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.

The invention provides circuits and methods for estimating and correcting nonlinear error in analog to digital converters that is introduced by nonlinear circuit elements, for example one or more residue amplifiers in a pipelined analog to digital converter integrated circuit. In a preferred method of the invention, pseudo random calibration sequences are introduced into the digital signal to be converted by a flash digital to analog converter in one or more initial stages of the pipelined analog to digital converter circuit. A digital residue signal of the output of the one or more initial pipelined analog to digital converter stages is sampled. Intermodulation products of the pseudo random calibration sequences that are present in the digital residue signal are determined to estimate nonlinear error introduced by the residue amplifier in the one or more stages. A digital correction signal is provided to the output of the one or more stages to cancel estimated nonlinear error.

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San Diego, CA, United States of America

Andrea Panigada