Ihp Gmbh-innovations for High Performance Microelectronics/leibniz-institut Fur Innovative Mikroelektronik

Andrea Malignaggi

Adel Fatemi

Aniello Franzese

Christoph Herold

A method for channel aggregation and single sideband transmission executed in a broad-band communication system is suggested in which only I and Q versions of a purely sinusoidal local oscillator signals are needed, easing the system scaling when large numbers of channels must be aggregated. In addition to that, instead of phase shifting of an intermediate frequency broadband signal rather two intermediate frequency broadband signals are generated, which are phase shifted by +90° or by −90°. As a result, the problems of frequency dependent phase shifting explained in the background section is not relevant for the method according to the present disclosure. Also, a corresponding method for image reject reception and channel separation as well as a transmitter and receiver for performing the methods are suggested.

Method and apparatus for channel aggregation and single sideband transmission

A switchable combiner and/or splitter circuit comprising at least two Wilkinson elements is suggested. The switchable circuit comprises one first terminal and for each Wilkinson element one pair of second terminals associated with the corresponding Wilkinson element. Each Wilkinson element connects the first terminal with the associated pair of second terminals. Each Wilkinson element includes a switchable component enabling selectively activating the associated pair of second terminals. The proposed solution combines a Single-Pole-Double-Through switch and a Wilkinson element and, thus, reduces the chip area required for integrating the circuit.

Switchable combiner and/or splitter circuit comprising Wilkinson elements

An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal is suggested. The apparatus comprises a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback loop forming a CDR loop. The voltage-controlled oscillator outputs a clock signal that is provided to the phase detector. The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit configured to receive the input signal and to generate two output signals having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate configured to receive the output signals from the interleave circuit and to generate an enable signal for the phase detector indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

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Frankfurt-am-Main, Germany

Andrea Malignaggi