Stmicroelectronics S.r.l.

Andrea Lodi

Luca Ciccarelli

Fabio Campi

Mario Toma

Roberto Antonio Canegallo

Roberto Guerrieri

Roberto Giansante

Andrea Cappelli

Luca Magagni

Carlo Chiesa

An embodiment of the invention relates to a T-switch for connecting first, second and third lines and comprising an input section in turn including first, second and third input pass transistors, each connecting a respective line with a first internal node of the T-switch, an output section in turn including first, second and third output pass transistors, each connecting a respective line with a second internal node of the T-switch, and a single buffer stage connected to a first and a second voltage reference and inserted between the first and second internal node.

T-switch buffer, in particular for FPGA architectures

A switch block suitable to realize the connection between interconnection lines connected thereto of the type comprising at least a switching block connected to the interconnection lines and including at least a buffer stage in turn connected to a plurality of transistors. The switch block comprises a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.

Switch block and corresponding switch matrix, in particular for FPGA architectures

A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.

Switch block for FPGA architectures

A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.

Digital architecture for reconfigurable computing in digital signal processing

An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.

Growing community of inventors

Castel San Pietro, Italy

Andrea Lodi