Cadence Design Systems, Inc.

Andrea Iabrudi Tavares

Fabiano Cruz Peixoto

Lawrence Loh

Artur Melo Mota Costa

Chung-Wah Norris Ip

Chien-Liang Lin

Breno Rodrigues Guimaraes

Marcus Vinicius Da Mata Gomes

Xiaoyang Sun

Alberto Manuel Arias Drake

Regina Mara Amaral Fonseca

Laiz Lipiainen Santos

Nathália Peixoto Reis

Tamires Vargas Campanema Franco Santos

Claudionor Jose Nunes Coelho, Jr

Patricia Sette Câmara Haizer

Tamires Vargas Capanema Franco Santos

Lucas Ferreira De Melo Diniz

Caio Araujo Texeira Campos

The present disclosure relates to a computer-implemented method for use in an electronic design. The method may include receiving, using at least one processor, an electronic design and analyzing the electronic design. The method may further include generating one or more preconditions representative of metastability effects at the output of at least one synchronizer associated with the electronic design. The method may also include generating, based upon, at least in part, the one or more preconditions, one or more properties configured to analyze a propagation of the metastability effects associated with the at least one synchronizer.

Systems and methods for automatic formal metastability fault analysis in an electronic design

Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques

Disclosed are techniques for implementing graph-driven verification and debugging of an electronic design. These techniques identify a pair of interest that comprises a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof. A boundary for relevant driver identification (RDI) operations may be identified for normal termination of the performance of one or more RDI operations. A debug graph may then be generated and stored at least by performing one or more RDI operations for at least the pair of interest based in whole or in part upon the boundary for RDI operations.

Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design

Various mechanisms identify an electronic design model and determine a data propagation diagram by receiving a set of path property sources or destinations, determine a set of helper properties for the data propagation diagram by traversing at least a portion of the data propagation diagram, and verify the electronic design model by examining one or more helper properties and determining verification of the one or more helper properties leads to concrete results to generate verification results. Data propagation diagrams may be annotated with verification results to show verification progresses, highlight sources of complexity, and be further synchronized with waveform displays of one or more traces. Search space may be trimmed during a verification flow to enhance performance of verification engine(s). New start states closer to the final state than the default state may be identified during verification and used to enhance performance of the verification engine.

Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow

Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components may be duplicated into the one or more duplicated electronic design components. One or more CDC effect models are automatically injected into the representation by adding the one or more CDC effect models along one or more paths in the representation. Proof results are generated at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models that are automatically injected into the representation.

Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths

Growing community of inventors

Belo Horizonte, Brazil

Andrea Iabrudi Tavares