Infineon Technologies Ag

Andrea Beit-Grogger

Josef Riegebauer

Helmut Koroschetz

An interface apparatus having a first and a second buffer storage unit, the first buffer storage unit being associated with a first domain and the second buffer storage unit being associated with a second domain, and the buffer storage units being connected to one another for transmitting data. Each of the storage units is of two-stage design and respectively has a first and a second memory, the first and second buffer storage units are connected by unit of connections between the second memory in one buffer storage unit and the first memory in the other buffer storage unit, and data from one domain being written to the first memory and then to the second memory when a transmission operation is no longer pending between the domains.

Interface circuit

Integrated circuit having security-critical circuit components arranged in a lower plane, data lines arranged in an upper plane, situated at least in part above the security-critical circuit components arranged in the lower plane, and connected to the security-critical circuit components, and a detector circuit that identifies an attack on the integrated circuit. The detector circuit has a transmitting device that transmits predetermined test data into the security-critical circuit components arranged in the lower plane, a receiving device that receives the data processed by the security-critical circuit components arranged in the lower plane, and an evaluation device that compares the received data with expected data and that ascertains any non-correspondence. The data lines carry the predetermined test data that is transmitted by the transmitting device and is processed by the security-critical circuit components.

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Andrea Beit-Grogger