Texas Instruments Corporation

Andre Szczepanek

Denis R Beaudoin

Iain Craig Robertson

Denis Roland Beaudoin

Stephen J Hubbins

Keith Balmer

Michael Stephen Harwood

Philip John Moyse

Derek Colman

Steven P Marshall

George Buchanan

Martin Yu Li

Travis M Scheckel

David G England

David Norvall

The present invention relates to pre-distortion in transmitter circuits and provides a circuit for introducing pre-distortion into the output of a transmitter, wherein said pre-distortion comprises a pre-cursor, a cursor and a post-cursor, the circuit comprising: a first driver arranged to switch an output drive between said pre-cursor and said cursor; a second driver arranged to switch an output drive between said post-cursor and said cursor; a third driver arranged to switch an output drive between a positive cursor drive and a negative cursor drive. The arrangement provided give flexibility when setting the pre-cursor, cursor and post-cursor levels.

Transmitter including pre-distortion

High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

Rapid I/O traffic system

A network switch system () is disclosed, in which a plurality of switch fabric devices () are interconnected according to a ring arrangement, each of the switch fabric devices () including therein switch interfaces () coupled to corresponding network switches (). Each switch fabric device includes a plurality of ring paths (), each of which is associated with a receive ring interface (R) and a transmit ring interface (X). Each ring path () includes a circular buffer () having a plurality of entries, each of which is associated with valid logic (). The valid logic () for each entry presents valid signals on valid lines (WV, RV) to the receive and transmit domains of the ring path (), and receives signals on write and read word request lines (WRW, RDW) therefrom. Control of the access to the circular buffer () is made according to the write and read word request lines (WRW, RDW) for the corresponding entries of the circular buffer () to which write pointers and read pointers point. The write word request line (WRW) sets the valid lines (WV, RV) for the corresponding entry in each of the two clock domains, while the read word request line (RDW) resets these valid lines (WV, RV) for that entry. Differences in clock frequency between the receive and transmit clock domains are thus compensated, with a minimum latency.

Communications interface between clock domains with minimal latency

The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of the invention, each incoming broadcast frame of data has an associated reference mask to indicate through which of a number of channels the frame of data is to be transmitted.

Order broadcast management (IOBMAN) scheme

The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of the invention, each incoming frame of data is packed and stored in blocks of no more than a predetermined block size, each block have an associated tag of control data and an associated pointer stored in a pointer memory for locating the block of data.

Packet memory management (PACMAN) scheme

Network switching systems ( ) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices ( ) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device ( ) having two full-duplex gigabit ports. According to one aspect of the invention, the switches ( ) are connected in a ring using their respective gigabit ports, with each of the switches ( ) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches ( ) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches ( ), or until the packet returns to the original switch ( ) which, upon detecting its own Ring ID value, filters or discards the packet. According to another aspect of the invention, switches ( ) have their gigabit ports connected to a crossbar-matrix switch ( ); pretags added by the switches to their received packets indicate the crossbar ports to which the packets are addressed. According to another aspect of the invention, each of the switches ( ) applies flow control over the gigabit ports in response to a message occupying more buffer space than remaining buffers; this permits buffer space to be utilized when traffic permits, without allowing a small minority of channels to adversely affect others.

Modular interconnection of network switches

Network switching systems ( ) for use in an Ethernet network are disclosed. Each of the switching systems includes switch devices ( ) supporting multiple (e.g., eight) local ports, and one gigabit high-speed port; each of the high-speed ports are full-duplex ports. Each switching system also includes a gigabit switch device ( ) having two full-duplex gigabit ports. According to one aspect of the invention, the switches ( ) are connected in a ring using their respective gigabit ports, with each of the switches ( ) having a Ring ID value. Upon receipt of a message packet at one of its local ports, the switches. ( ) attach a pretag with the Ring ID value upon the packet, and begin forwarding the packet around the ring until the destination address is registered with one of the switches ( ), or until the packet returns to the original switch ( ) which, upon detecting its own Ring ID value, filters or discards the packet. According to another aspect of the invention, switches ( ) have their gigabit ports connected to a crossbar-matrix switch ( ); pretags added by the switches to their received packets indicate the crossbar ports to which the packets are addressed. According to another aspect of the invention, each of the switches ( ) applies flow control over the gigabit ports in response to a message occupying more buffer space than remaining buffers; this permits buffer space to be utilized when traffic permits, without allowing a small minority of channels to adversely affect others.

Ring configuration for network switches

The present invention includes an improved switching device ( ) which operates in a shared media environment. The switching device ( ) in accordance with the present invention includes a tag header processing means ( ) operable to insert a tag header into frames that enter the switching device ( ) without a tag header and CRC processing means ( ) operable to calculate a CRC for the frame excluding the tag header for use while the frame is being processed within the switching device ( ). The tag header processing means ( ) is further operable, when the internal switch processing of the frame is completed and the frame is ready to be transmitted, to determine whether or not the frame should be transmitted without a tag header and removing the tag header if it is not. The CRC processing means ( ) is further operable to calculate a CRC for the frame when the internal processing of the frame is completed and, if the frame was originally received with a tag header, to corrupt the CRC if needed based on parity bits included in the tag header when the frame was received.

VLAN tag transport within a switch

A data aliginmentation apparatus and method in a LAN adapter. The arrangement includes a data aligner mechanism and a transfer control mechanism that transfer data between this RAM and a PCI bus. A transfer control mechanism pre-calculates the control parameters for the aligner/data-pipe, creates the necessary byte enables for data transfers, and determines the number of transfers needed. This allows the data aligner to create a stream of data words for any arbitrary byte transfer with full PCI data streaming (one 32 bit word every PCI clock cycle). The Data Aligner provides a shifter and data-pipe that is used to convert the RAMs 64 bit words into PCIs 32 bit words. It is bidirectional and is used to convert 64 bit data from the RAM into 32 bit PCI word(s) and vice versa.

Network adapter with data aligner

This invention relates to an improved LAN adapter. The LAN adapter includes a time division multiplex (TDM) ported RAM. The RAM is used to provide both network data FIFOs and control data storage in a single memory element. The network and peripheral components are able to access the same memory, but at different times in the cycle, thereby minimizing the component count and optimizing the operation of the adapter.

Network adapter having single ported memory which is accessible by

A local area network ('LAN') controller operable in an IEEE 802.3u network and an IEEE 802.12 network. A common physical connector is used for both standards, attached to an attachment medium such as a card. An 802.3u circuit is attached to the card, implementing the following 802.3u functions: A media access controller ('MAC') layer, and a physical media independent ('PMI') layer that provides the IEEE 802.3u media independent interface ('MII'). An 802.12 circuit is also attached to the card, implementing the following IEEE 802.12 functions: An LLC layer, an MAC layer, and a PMI layer, providing an MII to a device implementing an 802.12 physical media dependent ('PMD') layer. A circuit coupled to the 802.12 circuit multiplexes, according to a predetermined strategy, 802.12 PMI to PMD signals over the physical connector and, alternatively, communicates 802.3u MII signals between the 802.3u circuit and the physical connector.

Multi-protocol local area network controller

A data alignmentation apparatus and method in a LAN adapter. The arrangement includes a data aligner mechanism and a transfer control mechanism that transfer data between this RAM and a PCI bus. A transfer control mechanism pre-calculates the control parameters for the aligner/data-pipe, creates the necessary byte enables for data transfers, and determines the member of transfers needed. This allows the data aligner to create a stream of data words for any arbitrary byte transfer with full PCI data streaming (one 32 bit word every PCI clock cycle). The Data Aligner provides a shifter and data-pipe that is used to convert the RAMs 64 bit words into PCIs 32 bit words. It is bidirectional and is used to convert 64 bit data from the RAM into 32 bit PCI word(s) and vice versa.

Adapter having data aligner including register being loaded to or from

A communications network adapter of the type coupling a computer, in which the computer includes a microprocessor, main memory and a system bus, that controls host interrupts in a manner to improve system performance. The adapter includes a buffer memory for storing data to be transferred between the bus an the network, and a transfer controller that controls the transfer of data between the main memory and the buffer memory and between the network and the buffer memory. The adapter also includes an interrupt controller that monitors predetermined events relating to data transfer between the computer and the network, and that causes the sending of interrupt signals to the microprocessor. Interrupt signals cause the microprocessor to initiate processing associated with the transfer of data between the computer and the network. According to one aspect of the invention the adapter includes an interrupt pacing timer that prevents the sending of interrupts to the microprocessor from the adapter for predetermined time after an interrupt acknowledgement signal is received from the microprocessor. According to another aspect of the invention an interrupt threshold counter is provided that prevents the sending of interrupts to the microprocessor until a predetermined plurality of frames are transmitted.

Data transfer interrupt pacing

A data communications system memory interface circuit (32) is provided which operates within an adapter circuit (10). Adapter circuit (10) comprises a communications processor (28), a system interface (30) and a protocol handler (20) coupled together by an adapter bus (26). Communications processor (28) accesses an external memory (38) through a memory interface (32). Memory interface (32) comprises a map register circuit (36) which comprises a number of map registers (44 through 56). The map registers (44 through 56) each are operable to store a portion of a twenty bit address which may be selected by a multiplexer (42) responsive to control signals generated by a control logic circuit (40). The address portion stored in the map registers (44 through 56) are added to a remaining portion of an address to form a complete twenty bit remapped address. In this manner, communications processor (28), using a sixteen bit internal address bus, can access a twenty bit addressable memory space within external memory (38). System interface (30) comprises an address register circuit (34) which allows for the accessing of arbitrary twenty bit addresses or the accessing of addresses using page address numbers and offset values. The protocol handler (20) comprises a page address register (24) which allows for the accessing of external memory (38) on one kilobyte page boundaries.

Data communications system with address remapping for expanded external

Circuitry for switching between a first and second clock signal is provided having a first local clock circuit 202, a first synchronizing circuit 200 connected to said first clock circuit 202, a first delay circuit 206a-d connected to said first synchronizing circuit 200 and said first clock circuit 202, a second delay circuit 206e, 210, connected to said first delay circuit 206a-d and said first clock circuit 202, a first logic circuit 220 connected to said first 206a-d and second 206e, 210 delay circuits and said first synchronizing circuit 200, a second local clock circuit 102, a second synchronizing circuit 100 connected to said second clock circuit 102, a third delay circuit 106, 108, 110, connected to said second synchronizing circuit 100 and said second clock circuit 102, a second logic circuit 104 connected to said second clock circuit 102 and a portion of said third delay circuit 106, 108, 110, a third logic circuit 120 connected to said third delay circuit 106, 108, 110, and said second clock circuit 102, and a multiplexer 16 connected to said first 220 and third 120 logic circuits. The method of the present invention switches between a first 19 and second 21 clock signal by detecting a change in a signal 23 indicative of need to switch from said first clock signal to said second clock signal (or vice vers. a) 302, generating at least one local control signal 70, 72 responsive to said detection 304, deselecting a first in use clock signal 306 responsive to a first local control signal, selecting the second clock signal 308 for use responsive to a second local control signal, and switching to the non-used (second) clock signal after a preselected delay 310 based upon said second clock signal and said detection of said change in said signal.

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Bedford, United Kingdom

Andre Szczepanek