Infineon Technologies Ag

Globalfoundries U.S. Inc.

Qimonda Ag

Andre Sturm

John J Ellis-Monaghan

Vibhor Jain

Siva P Adusumilli

Mark Levy

Christopher P Miller

Wolfgang Hokenmaier

Michael A Killian

Harald Streif

Jochen Hoffman

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.

Photodiode and/or PIN diode structures

The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.

Power savings for memory with error correction mode

A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.

Reducing leakage current in memory device using bitline isolation

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Essex Junction, VT, United States of America

Andre Sturm